CY28346
Pin Description
Pin
Name
PWR
I/O
I
Description
2
XIN
Oscillator Buffer Input. Connect to a crystal or to an external clock.
3
XOUT
VDD
VDD
VDDP
VDD
O
Oscillator Buffer Output. Connecttoacrystal. Donotconnectwhen anexternal
clock is applied at XIN.
52, 51, 49, 48, CPUT(0:2),
CPUC(0:2)
PCI(0:6)
O
O
O
Differential Host Output Clock Pairs. See Table 1 for frequency/functionality.
PCI Clock Outputs. Are synchronous to 66IN or 3V66 clock. See Table 1.
45, 44
10, 11, 12, 13,
16, 17, 18
5, 6, 7
PCIF (0:2)
33MHz PCI Clocks. y2 copies of 66IN or 3V66 clocks that may be free running
(not stopped when PCI_STP# is asserted LOW) or may be stoppable depending
on the programming of SMBus register Byte3,Bits (3:5).
56
42
REF
VDD
VDD
O
I
Buffered Output Copy of the Device’s XIN Clock.
IREF
Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and VSSIREF.
28
VTT_PG#
VDD
I
Qualifying Input that Latches S(0:2) and MULT0. When this input is at a logic
LOW, the S(0:2) and MULT0 are latched.
39
38
33
35
48MUSB
48MDOT
VDD48
VDD48
VDD
O
O
O
O
Fixed 48 MHz USB Clock Outputs.
Fixed 48 MHZ DOT Clock Outputs.
3.3V 66 MHz Fixed-frequency Clock.
3V66_0
3V66_1/VCH
VDD
3.3V Clock Selectable with SMBus Byte0,Bit5, When Byte5,Bit5. When Byte
0,Bit 5 is at a logic 1, then this pin is a 48M output clock. When Byte0,Bit5 is a
logic 0, this is a 66M output clock (default).
25
43
PD#
VDD
I
Power-down Mode Pin. A logic LOW level causes the device to enter a
PU power-down state. All internal logic is turned off except for the SMBus logic. All
output buffers are stopped.
MULT0
I
PU
Programming Input Selection for CPU Clock Current Multiplier.
55, 54
29
S(0,1)
I
I
I
I
Frequency Select Inputs. See Table 1.
SDATA
Serial Data Input. Conforms to the SMBus specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
30
40
SCLK
S2
I
I
Serial Clock Input. Conforms to the SMBus specification.
VDD
I
T
Frequency Select Input. See Table 1. This is a Tri-level input which is driven
HIGH, LOW or driven to a intermediate level.
34
PCI_STP#
VDD
I
PCI Clock Disable Input. When asserted LOW, PCI (0:6) clocks are synchro-
PU nously disabled in a LOW state. This pin does not effect PCIF (0:2) clocks’
outputs if they are programmed to be PCIF clocks via the device’s SMBus
interface.
53
CPU_STP#
VDD
I
CPU Clock Disable Input. When asserted LOW, CPUT (0:2) clocks are
PU synchronously disabled in a HIGH state and CPUC(0:2) clocks are synchro-
nously disabled in a LOW state.
24
66IN/3V66_5
VDD
VDD
I/O Input Connection for 66CLK(0:2) Output Clock Buffers if S2 = 1, or output
clock for fixed 66-MHz clock if S2 = 0. See Table 1.
21, 22, 23
66B(0:2)/
3V66(2:4)
O
3.3V Clock Outputs. These clocks are buffered copies of the 66IN clock or fixed
at 66 MHz. See Table 1.
1,8,14, 19, 32,
37, 46, 50
VDD
PWR 3.3V Power Supply.
4,9,15, 20, 27,
31, 36, 47
VSS
PWR Common Ground.
41
VSSIREF
PWR Current Reference Programming Input for CPU Buffers. A resistor is
connected between this pin and IREF. This pin should also be returned to device
VSS
.
26
VDDA
–
PWR Analog Power Input. Used for phase-locked loops (PLLs) and internal analog
circuits. It is also specifically used to detect and determine when power is at an
acceptable level to enable the device to operate.
Rev 1.0,November 24, 2006
Page 2 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
