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CY28341OCT 参数 Datasheet PDF下载

CY28341OCT图片预览
型号: CY28341OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 通用单芯片时钟解决方案VIA P4M266 / KM266 DDR系统 [Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341  
Table 6. Dial-A-Ratio™ AGP(0:2)  
00  
Frequency Selection Default  
01  
2/1  
2.5/1  
3/1  
10  
11  
Byte 5: SDR/DDR Clock Register  
Bit  
@Pup  
Pin#  
Name  
Description  
7
0
45  
BUF_IN  
threshold  
voltage  
DDR Mode, BUF_IN threshold setting. 0 = 1.15V, 1 = 1.05VSDR Mode, BUF_IN  
threshold setting. 0 = 1.35V, 1 = 1.25V  
6
5
1
1
46  
FBOUT  
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
29,30  
DDRT/C5/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(10,11)  
4
3
2
1
0
1
1
1
1
1
31,32  
35,36  
37,38  
41,42  
43,44  
DDRT/C4/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(8,9)  
DDRT/C3/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(6,7)  
DDRT/C2/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(4,5)  
DDRT/C1/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(2,3)  
DDRT/C0/SD 1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.  
RAM(0,1)  
Byte 6: Watchdog Register  
Bit @Pup Pin# Name  
Description  
7
6
1
0
26 SRESET# 1 = Pin 26 is the input pin as PD# signal. 0 = Pin 26 is the output pin as SRESET# signal.  
Frequency This bit allows setting the Revert Frequency once the system is rebooted due to Watchdog time  
Revert  
out only.0 = selects frequency of existing H/W setting1 = selects frequency of the second to last  
S/W setting (the software setting prior to the one that caused a system reboot).  
5
4
0
0
WDTEST WD-Test, ALWAYS program to “0.”  
WD Alarm This bit is set to “1” when the Watchdog times out. It is reset to “0” when the system clears the  
WD time stamps (WD3:0).  
3
2
1
0
0
0
0
0
WD3  
WD2  
WD1  
WD0  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7.  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7.  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7.  
This bit allows the selection of the time stamp for the Watchdog timer. See Table 7.  
Table 7. Watchdog Time Stamp  
WD3  
WD2  
WD1  
WD0  
FUNCTION  
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
Off  
1 second  
2 seconds  
3 seconds  
4 seconds  
5 seconds  
6 seconds  
7 seconds  
8 seconds  
9 seconds  
10 seconds  
Rev 1.0,November 20, 2006  
Page 7 of 19