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CY28341OCT 参数 Datasheet PDF下载

CY28341OCT图片预览
型号: CY28341OCT
PDF下载: 下载PDF文件 查看货源
内容描述: 通用单芯片时钟解决方案VIA P4M266 / KM266 DDR系统 [Universal Single-Chip Clock Solution for VIA P4M266/KM266 DDR Systems]
分类和应用: 晶体外围集成电路光电二极管双倍数据速率时钟
文件页数/大小: 19 页 / 264 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
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CY28341  
Table 4. Byte Read and Byte Write Protocol  
Byte Write Protocol  
Byte Read Protocol  
Description  
Start  
Bit  
1
Description  
Start  
Bit  
1
2:8  
9
Slave address – 7 bits  
Write  
2:8  
9
Slave address – 7 bits  
Write  
10  
Acknowledge from slave  
10  
Acknowledge from slave  
11:18  
Command Code – 8 bits “1xxxxxxx” stands for  
byte operationbit[6:0] of the command code  
represents the offset of the byte to be accessed  
11:18  
Command Code – 8 bits “1xxxxxxx” stands for  
byte operationbit[6:0] of the command code  
represents the offset of the byte to be accessed  
19  
20:27  
28  
Acknowledge from slave  
Byte Count – 8 bits  
Acknowledge from slave  
Stop  
19  
20  
Acknowledge from slave  
Repeat start  
21:27  
28  
Slave address – 7 bits  
Read  
29  
29  
Acknowledge from slave  
Data byte from slave – 8 bits  
Not Acknowledge  
Stop  
30:37  
38  
39  
Serial Control Registers  
Byte 0: Frequency Select Register  
Bit  
7
@Pup  
0
Pin#  
Name  
Reserved  
FS2  
Description  
Reserved  
6
H/W Setting  
H/W Setting  
H/W Setting  
0
21  
10  
1
For Selecting Frequencies see Table 1.  
For Selecting Frequencies see Table 1.  
For Selecting Frequencies see Table 1.  
5
FS1  
4
FS0  
3
If this bit is programmed to “1,” it enables Write to bits (6:4,1) for  
selecting the frequency via software (SMBus). If this bit is  
programmed to a “0,” it enables only Read of bits (6:4,1), which  
reflects the hardware setting of FS(0:3).  
2
H/W Setting  
11  
SELSDR_DDR Only for reading the hardware setting of the SDRAM interface  
mode, status of SELSDR_DDR# strapping.  
1
0
H/W Setting  
H/W Setting  
20  
7
FS3  
For Selecting frequencies see Table 1ꢁ  
SELP4_K7  
Only for reading the hardware setting of the CPU interface mode,  
status of SELP4_K7# strapping.  
Byte 1: CPU Clocks Register  
Bit @Pup Pin#  
Name  
Description  
7
6
5
4
3
0
1
1
1
1
MODE  
0 = Down Spread. 1 = Center Spread. See Table 9.  
1 = Enable (default). 0 = Disable  
SSCG  
SST1  
SST0  
Select spread bandwidth. See Table 9.  
Select spread bandwidth. See Table 9.  
48,49 CPUCS_T, CPUCS_C 1 = output enabled (running). 0 = output disabled asynchronously in a LOW  
state.  
2
1
53,52  
CPUT/CPUOD_T  
CPUC/CPUOD_C  
1 = output enabled (running). 0 = output disable.  
Rev 1.0,November 20, 2006  
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