CY28341
Pin Description[2] (continued)
Pin
Name
PWR
I/O
Description
11
21
SELSDR_DDR#/PCI VDDPCI I/O Power-on Bidirectional Input/Output. At power-up, SELSDR_DDR is the
1
PD input. When the power supply voltage crosses the input threshold voltage,
SELSDR_DDR state is latched and this pin becomes PCI clock
output.SelSDR_DDR#. = 0, DDR Mode. SelSDR_DDR#. = 1, SDR Mode.
FS2/24_48M
VDD48M I/O Power-on Bidirectional Input/Output. At power-up, FS2 is the input. When
PD the power supply voltage crosses the input threshold voltage, FS2 state is
latched and this pin becomes 24_48M, a SIO programmable clock output.
6
AGP0
AGP2
IREF
VDDAG
P
O
O
I
AGP Clock Output. Is synchronous to CPU clocks. See Table 1.
8
VDDAG
P
AGP Clock Output. Is synchronous to CPU clocks. See Table 1.
25
28
Current reference programming input for CPU buffers. A precise resistor is
attached to this pin, which is connected to the internal current reference.
SDATA
I/O Serial Data Input. Conforms to the Philips I2C specification of a Slave
Receive/Transmit device. It is an input when receiving data. It is an open drain
output when acknowledging or transmitting data.
27
26
SCLK
I
Serial Clock Input. Conforms to the Philips I2C specification.
PD#/SRESET#
I/O Power-down Input/System Reset Control Output. If Byte6 Bit7 = 0, this pin
PU becomes a SRESET# open drain output, and the internal pulled up is not active.
See system reset description. If Byte6 Bit7 = 1 (default), this pin becomes PD#
input with an internal pull-up. When PD# is asserted LOW, the device enters
power-down mode. See power management function.
45
46
BUF_IN
FBOUT
If SelSDR_DDR#.= 0, 2.5V CMOS type input to the DDR differential buffers.If
SelSDR_DDR#.= 1, 3.3V CMOS type input to the SDR buffer.
If SelSDR_DDR#.= 0, 2.5V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the DDRT(0:5) signals.If
SelSDR_DDR#.= 1, 3.3V single ended SDRAM buffered output of the signal
applied at BUF_IN. It is in phase with the SDRAM(0:11) signals
5
VDDAGP
VDDC
3.3V Power Supply for AGP clocks
3.3V Power Supply for CPUT/C clocks
3.3V Power Supply for PCI clocks
3.3V Power Supply for REF clock
2.5V Power Supply for CPUCS_T/C clocks
3.3V Power Supply for 48M
51
16
55
50
22
23
VDDPCI
VDDR
VDDI
VDD48M
VDD
3.3V Common Power Supply
34,40
VDDD
If SelSDR_DDR#.= 0, 2.5V Power Supply for DDR clocksIf SelSDR_DDR#.=
1, 3.3V Power Supply for SDR clocks.
9
VSSAGP
VSSPCI
VSSC
Ground for AGP clocks
Ground for PCI clocks
Ground for CPUT/C clocks
Ground for DDR clocks
Ground for 48M clock
Ground for ICPUCS_T/C clocks
Common Ground
13
54
33,39
19
VSSD
VSS48M
VSSI
47
24
VSS
Note:
2. PU = internal Pull-up. PD = internal Pull-down. Typically = 250 kW (range 200 kW to 500 kW).
Rev 1.0,November 20, 2006
Page 3 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
