CY28341
Byte 1: CPU Clocks Register (continued)
1
1
53,52
CPUT/C
In K7 mode, this bit is ignored.In P4 mode, 0 = when PD# asserted LOW,
CPUT stops in a HIGH state, CPUC stops in a LOW state. In P4 mode, 1 =
when PD# asserted LOW, CPUT and CPUC stop in High-Z.
0
1
11
MULT0
Only For reading the hardware setting of the Pin11 MULT0 value.
Byte 2: PCI Clock Register
Bit
7
@Pup
Pin#
Name
PCI_DRV
PCI_F
PCI6
Description
0
1
1
1
1
1
1
1
PCI clock output drive strength 0 = Normal, 1 = increase the drive strength 20%.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
6
10
18
17
15
14
12
11
5
4
PCI5
3
PCI4
2
PCI3
1
PCI2
0
PCI1
Byte 3: AGP/Peripheral Clocks Register
Bit @Pup Pin#
Name
Description
7
0
21
24_48M
“0” = pin21 output is 24MHz. Writing a “1” into this register asynchronously changes the
frequency at pin21 to 48 MHz.
6
5
4
3
2
1
0
1
1
0
0
1
1
1
20
21
48MHz
24_48M
DASAG1
DASAG0
AGP2
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
6,7,8
6,7,8
8
Programming these bits allow shifting skew of the AGP(0:2) signals relative to their
default value. See Table 5.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
7
AGP1
6
AGP0
Table 5. Dial-a-Skew™ AGP(0:2)
DASAG (1:0)
AGP(0:2) Skew Shift
Default
00
01
–280 ps
10
+280 ps
11
+480 ps
Byte 4: Peripheral Clocks Register
Bit @Pup Pin#
Name
Description
7
1
20
48M
1 = normal strength, 0 = high strength
1 = normal strength, 0 = high strength
6
1
21
24_48M 1 = normal strength, 0 = high strength
1 = normal strength, 0 = high strength
5
4
3
2
1
0
0
0
1
1
1
1
6,7,8 DARAG1 Programming these bits allow modifying the frequency ratio of the AGP(2:0), PCI(6:1, F) clocks
relative to the CPU clocks. See Table 6.
6,7,8 DARAG0
1
56
1
REF0
REF1
REF0
REF1
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state.
1 = output enabled (running). 0 = output disabled asynchronously in a LOW state. (K7 Mode only.)
1 = normal strength, 0 = high strength
56
1 = normal strength, 0 = high strength (K7 Mode only.)
Table 6. Dial-A-Ratio™ AGP(0:2)
DARAG (1:0)
CU/AGP Ratio
Rev 1.0,November 20, 2006
Page 6 of 19
SPECTRALINEAR [ SPECTRALINEAR INC ]
