欢迎访问ic37.com |
会员登录 免费注册
发布采购

CY28326OC 参数 Datasheet PDF下载

CY28326OC图片预览
型号: CY28326OC
PDF下载: 下载PDF文件 查看货源
内容描述: FTG威盛PT880芯片组的串行 [FTG for VIA PT880 Serial Chipset]
分类和应用: 晶体外围集成电路光电二极管时钟
文件页数/大小: 22 页 / 224 K
品牌: SPECTRALINEAR [ SPECTRALINEAR INC ]
 浏览型号CY28326OC的Datasheet PDF文件第1页浏览型号CY28326OC的Datasheet PDF文件第2页浏览型号CY28326OC的Datasheet PDF文件第4页浏览型号CY28326OC的Datasheet PDF文件第5页浏览型号CY28326OC的Datasheet PDF文件第6页浏览型号CY28326OC的Datasheet PDF文件第7页浏览型号CY28326OC的Datasheet PDF文件第8页浏览型号CY28326OC的Datasheet PDF文件第9页  
CY28326  
Pin Definition (continued)  
Pin No.  
24  
Name  
VDD48  
AGP0/AGP2 VDDAGP  
PWR  
Type  
I
Description  
Power for 48MHz clock output.  
AGP Clock Output.  
25,29  
26  
O
*RatioSEL  
/AGP1  
VDDAGP  
I/O  
Power-on Bi-directional Input/output. At power up, RatioSel is  
the input. when the power supply voltage crosses the input  
threshold voltage, RatioSel state is latched and this pin becomes  
AGP clock output. Default pull-up.  
27  
28  
30  
31  
32  
VDDAGP  
VSSAGP  
SRESET#  
SCLK  
I
I
3.3V power supply for AGP clock output.  
Ground for AGP clock output.  
O
I
System Reset Control Output.  
Serial clock input. Conforms to the Philips I2C specification.  
Serial clock input. Conforms to the Philips I2C specification of a  
Slave Receive/Transmit device. it is an input when receiving data.  
It is open drain output when acknowledging or transmitting data.  
SDATA  
I/O  
33  
*VTT_PWRG  
D/PD#  
I
VTT_PWRGD: 3.3V LVTTL input to determine when FS[D:A],  
MODE, RatioSEL and 24_48_SEL inputs are valid and ready to  
be sampled.  
PD#: Invokes powerdown mode. Default Internal pull up.  
34  
35,36  
37  
VDDSRC  
25MHz[0:1]  
VSSSRC  
I
O
I
Power for 25 MHz clock output. 3.3V Power Supply.  
25 MHz Clock Output.  
VDDSRC  
Ground for 25 MHz clock output.  
CPU Clock outputs.  
39,38,42,41,45,44 CPU[T/C][0:2] VDDCPU  
O
I
40  
43  
46  
VDDCPU  
VSSCPU  
IREF  
Power for CPU clock output.  
Ground for CPU clock output.  
I
I
Current Reference. A precision resistor is attached to this pin,  
which is connected to the internal current reference.  
47  
48  
VSSA  
VDDA  
I
I
Ground for output.  
3.3V Power Supply for output  
Table 1. Frequency Table  
PLL Gear  
Constant  
(Million)  
FS(D:A)  
FS(3:0)  
0000  
0001  
0010  
0011  
0100  
0101  
0110  
0111  
1000  
1001  
1010  
1011  
1100  
1101  
1110  
1111  
CPU (MHz)  
AGP (MHz)  
73.3  
73.3  
73.3  
73.3  
66.7  
66.7  
66.7  
66.7  
67.3  
67.0  
67.0  
66.8  
66.7  
66.7  
66.7  
66.7  
PCI (MHz)  
36.6  
36.6  
36.6  
36.6  
33.3  
33.3  
33.3  
33.3  
33.6  
33.5  
33.5  
33.4  
33.3  
33.3  
33.3  
33.3  
SATA (MHz)  
25.0  
VCO (MHz)  
660.00  
586.68  
440.00  
733.33  
466.67  
533.33  
666.67  
600.00  
807.2  
110.0  
146.6  
220.0  
183.3  
233.3  
266.6  
333.3  
300.0  
100.9  
133.9  
200.9  
166.9  
100.0  
133.3  
200.0  
166.6  
25.00258122  
37.50387182  
75.00774365  
37.50387182  
75.00774365  
75.00774365  
75.00774365  
75.00774365  
18.75193591  
25.00258122  
37.50387182  
37.50387182  
18.75193591  
25.00258122  
37.50387182  
37.50387182  
25.0  
25.0  
25.0  
25.0  
25.0  
25.0  
25.0  
25.0  
25.0  
803.4  
25.0  
803.6  
25.0  
667.6  
25.0  
800.00  
800.00  
800.00  
666.67  
25.0  
25.0  
25.0  
Rev 1.0,November 20, 2006  
Page 3 of 22