CY28326
Byte 4: Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
48 MHz
48 MHz Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
24_48 MHz
PCI5
24_48 MHz Output Enable
0 = Disabled, 1 = Enabled
PCI5 Output Enable
0 = Disabled, 1 = Enabled
PCI4
PCI4 Output Enable
0 = Disabled, 1 = Enabled
PCI3
PCI3 Output Enable
0 = Disabled, 1 = Enabled
PCI2
PCI2 Output Enable
0 = Disabled, 1 = Enabled
PCI1
PCI1 Output Enable
0 = Disabled, 1 = Enabled
PCI0
PCI0 Output Enable
0 = Disabled, 1 = Enabled
Byte 5: Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
AGP2
AGP2 Output Enable
0 = Disabled, 1 = Enabled
6
5
4
3
2
1
0
1
1
1
1
1
1
1
AGP1
AGP10
25 MHz1
25 MHz0
PCIF2
AGP1 Output Enable
0 = Disabled, 1 = Enabled
AGP0 Output Enable
0 = Disabled, 1 = Enabled
25 MHz1 Output Enable
0 = Disabled, 1 = Enabled
25 MHz0 Output Enable
0 = Disabled, 1 = Enabled
PCIF2 Output Enable
0 = Disabled, 1 = Enabled
PCIF1
PCIF1 Output Enable
0 = Disabled, 1 = Enabled
PCIF0
PCIF0 Output Enable
0 = Disabled, 1 = Enabled
Byte 6: Control Register
Bit
7
@Pup
Name/Pin Affected
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
Description
0
0
0
0
1
0
0
0
Revision ID Bit 3
Revision ID Bit 2
Revision ID Bit 1
Revision ID Bit 0
Vendor ID Bit 3
Vendor ID Bit 2
Vendor ID Bit 1
Vendor ID Bit 0
6
5
4
3
2
1
0
Byte 7: Fract Aligner Control Register
Bit
@Pup
Name/Pin Affected
Description
7
1
PCI6
PCI6 Output Enable
0 = Disabled, 1 = Enabled
Rev 1.0,November 20, 2006
Page 7 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
