CY28326
Pin Definition
Pin No.
Name
PWR
Type
Description
1
**FSA/REF0 VDDREF
**FSB/REF1 VDDREF
VDDREF
I/O
Power-on Bi-directional Input/Output. At power-up, FSA is the
input. when VTT_PWRGD transitions to a logic high, FSA state is
latched and this pin becomes REF0, buffered output copy of the
device’s XIN clock. Default Internal pull down.
2
I/O
Power-on Bi-directional Input/Output. At power-up, FSB is the
input. when VTT_PWRGD transitions to a logic high, FSB state is
latched and this pin becomes REF1, buffered output copy of the
device’s XIN clock. Default Internal pull down.
3
4
I
I
3.3V Power supply for REF clock output.
XIN
VDDREF
Oscillator Buffer Input. Connect to a crystal or to an external
clock.
5
XOUT
VSSREF
VDDREF
O
Oscillator Buffer Input. Connect to a crystal. Do not connect
when an external clock is applied at XIN.
6
7
PWR
I/O
Ground for REF clock outputs
*FSC/PCIF0 VDDPCI
Power-on Bi-directional Input/ Output. At power up, FSC is the
input. When the VTT_PWRGD transitions to a logic high, FSC
state is latched and this pin becomes PCIF0. Default Internal pull
up.
8
9
*FSD/PCIF1 VDDPCI
I/O
I/O
Power-on Bi-directional Input/ Output. At power up, FSD is the
input. When the VTT_PWRGD transitions to a logic high, FSD
state is latched and this pin becomes PCIF. Default Internal pull
up.
*MODE/
PCIF2
VDDPCI
Power-on Bi-directional Input/ Output. At power up,
MODE/PCIF2 is the input. When the power up, MODE state is
latched and then pin9 becomes PCIF2, PCI clock output for PCI
Device.Default pull-up, See Table 2
10,17
11,18
VDDPCI
VSSPCI
I
3.3V power supply for PCI clock output.
Ground for PCI clock output.
PCI clock outputs.
I
12,13,14,15,16 PCI[0:4]
O
O
19
*(PCI_STP#) VDDPCI
Ratio0/PCI5
Ratio0 Output/PCI5 Output. At power up when RatioSel (pin 26)
strapping = “High” & MODE (pin 9) strapping=”High”, (PCI_STP#)
Ratio0/PCI5 becomes PCI5 clock output. At power up when
RatioSel (pin 26) strapping = “low” & MODE (pin 9) strapping
=”High”, (PCI_STP#)Ratio0/PCI5 becomes Ratio0 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio0/PCI5
becomes PCI_STP#, Default = “PCI5” see Table 2, Default
Internal pull up.
20
*(CPU_STP#) VDDPCI
Ratio1/PCI6
O
Ratio1 Output/PCI6 Output. At power up when RatioSel(pin 26)
strapping=“High”&MODE(pin9)strapping=”High”, (CPU_STP#)
Ratio1/PCI6 becomes PCI6 clock output. At power up when
RatioSel (pin 26) strapping = “low” & MODE(pin 9) strapping
=”High”, (PCI_STP#)Ratio1/PCI6 becomes Ratio1 output to
support North bridge over freq strapping function. Once
MODE(pin 9) strapping=”Low”, then (PCI_STP#)Ratio1/PCI6
becomes CPU_STP#, Default = “PCI6” see Table 2, Default
Internal pull up.
21
22
48 MHz
VDD48
O
48 MHz Clock Output.
**24_48_SEL/ VDD48
24_48 MHz
I/O
Power-on Bi-directional Input/output. At power up 24_48_SEL
is the input. When VTT_PWRGD is transited to logic high,
24_48_SEL state is latched and this pin becomes 24/48 MHz
output, Default 24_48_SEL= “0”, 48 MHz output.Default Internal
pull down.
23
VSS48
I
Ground for 48 MHz clock output.
Rev 1.0,November 20, 2006
Page 2 of 22
SPECTRALINEAR [ SPECTRALINEAR INC ]
