CXA2095S
Pin
No.
Symbol
Equivalent circuit
Description
JVCC
Internal reference current setting.
Connect to GND via a 15kΩ resistor.
41
42
43
IREF
20k
147
41
JVCC
Filter for V sync separation.
Connect to GND via a capacitor.
VSFIL
42
1k
JVCC
147
Sync signal input for V sync separation.
Input a 2Vp-p Y signal.
VSIN
43
20µ
JVCC
147
Sync signal input for H sync separation.
Input a 2Vp-p Y signal.
44 HSIN
44
10µ
SVCC
Y signal differential waveform output for VM
(Velocity Modulation). (7.1VDC, 2.0Vp-p) The
signal delayed for 250ns from YIN is output.
The delay time from YIN and the differential
coefficient of the output signal vary according to
sharpness f0 control.
45
VM
45
400µ
1k
Burst gate pulse output.
This pulse is a 0 to 3V positive polarity pulse.
While this pulse is gated near V-Sync for the
CXA2025S, it is constantly output for the
CXA2095S.
46
BGP
46
15k
1k
– 8 –
SONY [ SONY CORPORATION ]
