CXA2095S
Pin
No.
Symbol
Equivalent circuit
Description
JVCC
100µ
100
100
Connect a capacitor to generate the V sawtooth
wave.
33
SAWOSC
33
34
35
Power supply for the deflection block.
JVCC
JVCC
H drive signal output.
147
This signal is output with the open collector.
This pin goes high (OFF) during hold-down.
For the CXA2025S, this pin is low (ON) during
hold-down.
35
HDRIVE
20k
H deflection pulse input for H AFC.
JVCC
Input an about 5Vp-p pulse via a capacitor. Set
the pulse width to 10 to 12µs. This pin is also
used as the hold-down signal input for the HD
output, and if this pin is 1 [V] or less for a 7V
cycle or longer, the hold-down function operates
and the HD output goes to high (OFF).
4.2V
147
10k
60k
50µ 50µ
AFCPIN
/HOFF
36
36
10k
In addition, the RGB outputs are all blanked and
the status is returned to the I2C bus.
JVCC
Filter for H AFC.
Connect to GND via a capacitor. The H phase
can also be controlled from this pin by leading
current in and out of this capacitor.
As the pin voltage rises, the picture shifts to the
left; as the pin voltage drops, the picture shifts to
the right.
100
L2FIL
37
37
25µ
JVCC
1.2k
46k
38
AFCFIL
CR connection for the AFC lag-lead filter.
38
50µ
50µ
JVCC
10k
39 CERA
40 JGND
Connect the ×32fH VCO ceramic oscillator.
39
400µ
50µ
GND for the deflection block.
– 7 –
SONY [ SONY CORPORATION ]
