64Mbit – High Speed SDRAM (CAS2/150 MHz)
8Mx8 HSDRAM
Preliminary Data Sheet
HSDRAM Command Truth Table
CKE
Previous
/CS
/RAS /CAS /WE
DQM BA1, A10/
BA0 AP
A11,
A9
A8-A0
Function
Current
Cycle
Cycle
H
H
H
H
H
H
H
H
H
H
H
H
L
Mode Register Set
No Operation (NOP)
Bank Activate
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
L
H
H
L
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
Op Code (BA1=0, BA0=0)
X
X
X
X
X
Row Address
Write with Auto-Precharge
Write
H
H
H
H
H
L
BS
BS
BS
BS
X
1
0
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Column
L
L
Column
Read with Auto-Precharge
Read
L
H
H
L
1
Column
L
0
Column
Burst termination
H
H
H
L
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
Single Bank Precharge
Precharge All Banks
Auto-Refresh (CBR)
Self Refresh Entry
Self Refresh Exit
L
BS
X
L
L
H
X
X
X
X
X
X
X
X
X
X
L
H
H
X
L
L
X
H
X
L
NOP or DESEL
X
Device Deselect
H
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
Data Write/Output Enable
Data Mask/ Output Disable
X
H
L
X
H
L
NOP or DESEL
NOP or DESEL
X
H
X
X
X
H
H
X
X
X
X
X
X
X
X
X
H
X
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
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Revision 1.2
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
