64Mbit – High Speed SDRAM (CAS2/150 MHz)
Preliminary Data Sheet
8Mx8 HSDRAM
Operating Currents (TA = 0°C to 70°C)
Parameter
Operating Current
Symbol
ICC1A
Test Condition
Value
130
Units Notes
BL = 1, CL = 3, Read or Write,
CKE VIH(min), tRC = min., tCK = min.
mA
mA
mA
1
(One Bank Active)
Standby Current in Power Down
Mode (DRAM Precharged)
ICC2P
2.5
2.0
CKE VIL, tCK = min.,
Input Change Every Two Cycles
ICC2PS
CKE VIL, tCK = Infinity,
No Input Change
Standby Current in Non-Power
Down Mode (DRAM Precharged)
ICC2N
ICC2NS
ICC3N
35
12
65
mA
mA
mA
CKE VIH, tCK = min.
CKE VIH, tCK = Infinity
Device Deselected (DRAM
Active)
CKE VIH, tCK = min.,
Input Change Every Two Cycles
ICC3P
ICC4B
3
mA
mA
CKE VIL, tCK = min.,
Input Change Every Two Cycles
Burst Operating Current
(Both Banks Active)
BL = Full Page, CL = 2,3, Read or Write,
140
1,2
tRC = Infinity, tCK = min.
Auto (CBR) Refresh Current
Self Refresh Current
Notes:
ICC5F
ICC5D
ICC6
CL = 3, tCK = min., tRC = tRC(min).
CL = 3, tCK = min., tRC = 15.625 µs
CKE ꢀꢁꢂꢃ9ꢄꢀ1Rꢀ,QSXWꢀ&KDQJH
210
35
4
mA
mA
mA
3,4,5
3,4,5
1. The specified value is obtained with the outputs open.
2. The specified value is obtained when the programmed burst length is executed to completion without interruption by a subsequent burst read or
burst write cycle.
3. The specified value is valid when addresses are changed no more than once during tCK(min).
4. The specified value is valid when No Operation commands are registered on every rising clock edge during tRC(min).
5. The specified value is valid when data inputs (DQs) are stable during tRC(min).
Enhanced Memory Systems Inc., 1850 Ramtron Dr., Colo Spgs, CO 80921
PHONE: (800) 545-DRAM; FAX: (719) 488-9095; http://www.edram.com
2000 Enhanced Memory Systems. All rights reserved.
The information contained herein is subject to change without notice.
Revision 1.2
Page 7 of 20
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