SM2605 - 2Mx32 ESDRAM
AC CHARACTERISTICS (TA = 0°C to + 70°C)
1. After power is applied to VDD and VDDQ (simultaneously) and the clock is stable, an initial pause of 100µs is required. After the
100µs delay is satisfied and at least one DESEL is applied, a Precharge All Banks command must be given followed by a minimum of
four Auto (CBR) Refresh cycles before the Mode Register Set operation can begin.
2. For VDDQ = 3.3V, AC timing and IDD tests have VIL = 0V and VIH = 2.8V with the timing referenced to the VTT = 1.4V crossover
point. For VDDQ = 2.5V, AC timing and IDD tests have VIL = 0V and VIH = 2.4V with the timing referenced to the VTT = 1.2V
crossover point.
VTT
Clock
RT = 50 ohm
tSETUP tHOLD
Z0 = 50 ohm
Output
Input
CLOAD = 30pF
tOH
tAC
tLZ
VTT
Output
AC Output Load Circuit
3. AC measurements assume tT = 1ns.
4. In addition to meeting the transition rate specification, the clock and CKE must transition between VIH and VIL (or between VIL and VIH)
in a monotonic manner.
Rev. 1.6
7
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
