SM2605 - 2Mx32 ESDRAM
ESDRAM Command Truth Table
CKE
Previous
Cycle
BA1,
BA0
A10,
Current
Cycle
/CS
L
/RAS /CAS
/WE
L
DQM
X
A9
A8/AP
A7-A0
Function
Mode Register Set
Extended Mode Register Set
Bank Activate
H
H
H
H
H
H
H
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
H
L
L
L
L
L
Op Code (BA1=0, BA0=0)
Op Code (BA1=0, BA0=1)
Row Address
L
L
X
L
L
H
L
H
H
H
L
X
BS
BS
BS
BS
BS
X
Read
L
H
H
H
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
0
1
Column
Read with Auto-Precharge
Write
L
L
X
Column
L
L
X
0
Column
Write with Auto-Precharge
Burst Termination
L
L
L
X
1
Column
L
H
H
H
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Single Bank Precharge
Precharge All Banks
Auto-Refresh (CBR)
Self Refresh Entry
L
L
X
BS
X
L
L
L
X
H
X
X
X
X
X
X
X
X
X
X
X
L
L
H
H
X
X
L
L
L
X
X
Self Refresh Exit
H
X
X
L
NOP or DESEL
X
X
Device Deselect (DESEL)
No Operation (NOP)
Clock Suspend Mode Entry
Clock Suspend Mode Exit
Power Down Mode Entry
Power Down Mode Exit
Data Write/Output Enable
Data Mask/Output Disable
H
H
H
L
H
L
X
H
X
X
X
H
X
X
X
H
X
X
X
X
X
X
X
X
X
X
H
L
X
X
H
L
NOP or DESEL
NOP or DESEL
X
X
H
X
X
X
X
H
H
X
X
X
X
X
X
X
X
L
X
H
X
Pin Description
Symbol
CLK
Type
Input
Input
Function
Clock: All ESDRAM input signals are sampled on the positive edge of CLK.
CKE
Clock Enable: Activates the CLK signal when high and deactivates CLK internally. CKE low initiates
the Power Down, Suspend, and Self-Refresh modes.
/CS
Input
Chip Select: Active low /CS enables the command decoder and disables the command decoder when
high. When the command decoder is disabled, new commands are ignored but previous operations
continue.
/RAS, /CAS,
/WE
Input
Input
Input
Command Inputs: Sampled on the rising edge of CLK, these inputs define the command to be
executed.
BA1, BA0
Bank Address: This input defines to which of the 4 banks a given command is being applied. This
address input is also used to program the Mode Registers.
A10-A0
Address Inputs: A10-A0 defines the row address for the Bank Activate command. A7-A0 defines the
column address for Read and Write commands. A8/AP invokes the Auto-Precharge operation. During
manual Precharge commands, A8/AP low specifies a single bank precharge while A8/AP high
precharges all banks. The address inputs are also used to program the Mode Registers.
DQ31-DQ0
Input/
Data I/O: Data bus inputs and outputs. For Write cycles input data is applied to these pins and must
be set-up and held relative to the rising edge of clock. For Read cycles, the device drives output data
on these pins after the CAS latency is satisfied.
Output
DQM3-DQM0
Input
Data I/O Mask Inputs: DQM inputs mask write data (zero latency) and acts as a synchronous output
enable (2 cycle latency) for read data. In the optional mode set via the Extended Mode register, output
enable latency is one when CAS latency is one.
VDD, VSS
Supply
Supply
Power and ground for the input buffers and core logic.
VDDQ, VSSQ
Isolated power supply and ground for output buffers. VDDQ may be connected to either 3.3V or 2.5V
power.
Rev. 1.6
4
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
