SM2605 - 2Mx32 ESDRAM
Architecture
The ESDRAM architecture also offers the designer two
different register load strategies via the mode register set
for write cycles. In Write Transfer mode, the row register
cache is always loaded with the sense amplifier (DRAM
data) contents on a write command. This ensures coherency
between the row register and the DRAM array. This allows
read-modify-write cycles and simplified memory control
logic.
In No Write Transfer mode, the row register cache is not
loaded during writes. Data is written to the DRAM sense
amplifiers and the prior row contents are maintained in the
row register (for write page misses). If the on-chip page
hit/miss comparator determines that the write is to the same
row latched in the SRAM row register, the write updates
the row register as well as the DRAM sense amplifiers to
maintain coherency. No Write Transfer mode allows
immediate return to the prior cached read page without
otherwise incurring a page miss penalty. Write page
precharge and a bank activate times can be hidden during
cache reads. The ESDRAM fast precharge time minimizes
latency between the end of a write and the next read or
write miss cycle. If a read follows a write cycle, write
precharge time can be hidden.
The ESDRAM architecture combines four banks of fast
22.6ns DRAM with four banks of 10.6ns SRAM row
register cache on one chip to improve memory latency. On
a page read miss, a DRAM bank is activated and data is
developed by the DRAM sense amplifiers in 12ns. The
sense amplifiers now hold an entire row of data (8K bits).
On a read command, the entire row is latched into the
SRAM row register and the specified starting address is
output in 10.6ns (CAS Latency of one at clock frequencies
up to 83MHz, and CAS Latency of two up to 166MHz).
The architecture allows fast 10.6ns latency to any of the
constantly open rows on page hits.
Early auto-precharge can be performed since row data is
latched separately in the SRAM row register from the
DRAM sense amplifiers. The precharge time can be hidden
behind a burst read from cache. This minimizes subsequent
page miss latency. The auto-precharge begins one clock
cycle after the Read-AP command and completes early
enough to allow the next pipelined random access to
complete by the end of the current burst cycle.
At 166MHz, all but one cycle of the next random access
to any location in the same bank can be hidden to increase
sustained bandwidth by up to two times over standard
SDRAM. For interleaved burst read accesses, the entire
precharge time is hidden and output data can be driven
without any wait states.
Compatibility
By making the ESDRAM exactly pin-compatible with
JEDEC standard SDRAM, it is possible for the memory
controller to support both types of memory with a simple
mode selection. Both SDRAM and ESDRAM use identical
memory footprints on the planar and identical DIMM
module wiring. Systems designed to support both memory
types can provide two distinct price/performance points
and a simple field upgrade with the ESDRAM.
PINOUTS
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
DQ3
1
2
3
4
5
6
7
8
9
80
79
78
77
76
75
74
73
72
DQ28
VDDQ
DQ27
DQ26
VSSQ
DQ25
DQ24
VDDQ
DQ15
VDDQ
DQ4
DQ5
VSSQ
DQ6
DQ7
VDDQ
DQ16
DQ17
VSSQ
DQ18
10
11
12
71
70
69
DQ14
VSSQ
DQ13
DQ19
VDDQ
VDD
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
100 pin LQFP
14 x 20 mm
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQ12
VDDQ
VSS
VSS
VDD
DQ11
DQ10
VSSQ
DQ9
DQ20
DQ21
VSSQ
DQ22
DQ23
VDDQ
DQM0
DQM2
/WE
0.65 mm pitch
DQ8
VDDQ
NC
DQM3
DQM1
CLK
/CAS
/RAS
/CS
CKE
NC
BA0
NC
BA1
A8/AP
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Rev. 1.6
2
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
