■ Bit 0 is the read/write bit. If set to a 1, a read operation is being
performed by the master; otherwise, a write is intended.
Stop Condition
A stop condition is indicated to the FM24C16 when there is a
low to high transition of SDA while SCL is high. All operations to the
FM24C16 should end with a stop. In addition, any operation will be
aborted at any point when this condition occurs.
Word Address
After a slave device acknowledges the slave address on a write
operation, the master will place the word address on the bus. This
byte, in addition to the three page select bits from the slave address
byte, forms the address of the byte within the memory that is to be
written. This 11-bit value is latched in the internal address latch.
There is no word address specified during a read operation,
although the upper three bits of the internal latch are set to the
page select values in the slave address.
During the transmission of each data byte and before the
acknowledge cycle, the address in the internal latch is incremented
to allow the following byte to be accessed immediately. When the
last byte in the memory is accessed (at address hex 7FF), the
address is reset to 0. There is no alignment requirement for the
first byte of a block cycle — any address may be specified. There is
also no limit to the number of bytes that may be accessed in a
single read or write operation.
Data/Address Transfers
Data/address transfers take place during the period when SCL
is high. Except under the two conditions described above, the state
of the SDA line may not change while SCL is high. Address transfers
are always sent to the FM24C16, while data transfers may either be
sent to the FM24C16 (for a write) or to the bus master (for a
read).
Acknowledge
Acknowledge transfers take place on the ninth clock cycle
after each eight-bit address or data transfer. During this clock
cycle, the transmitter will release the SDA bus to allow the receiver
to drive the bus low to acknowledge receipt of the byte.
If the receiver does not acknowledge any byte, the operation is
aborted.
Data Transfer
After all address bytes have been transmitted, data will be
transferred between the FM24C16 and the bus master. In the case
of a read, the FM24C16 will place each of the eight bits on the bus
and then wait for an acknowledge from the bus master before
performing a read on the subsequent address. For a write
operation, the FM24C16 will accept eight bits from the bus master
and then drive the acknowledge on the bus.
All data and address bytes are transmitted most significant bit
(bit 7) first.
After the acknowledge of a data byte transfer, the bus master
may either begin another read or write on the subsequent byte,
issue a stop command to terminate the block operation, or issue a
start command to terminate the current operation and start a new
one.
Device Operation
Low Voltage Protection
When powering up, the FM24C16 will automatically perform
an internal reset and await a start signal from the bus master. The
bus master should wait TPUR (or TPUW ) after V reaches 4.5V
CC
before issuing the start for the first read or write access.
Additionally, whenever V falls below 3.5V (typical), the part goes
into its low voltage proteCcCtion mode. In this mode, all accesses to
the part are inhibited and the part performs an internal reset. If an
access was in progress when the power supply fails, it will be
automatically aborted by the FM24C16. When power rises back
above 4.5V, a start signal must be issued by the bus master to
initiate an access.
Slave Address
Figure 4. Slave Address
Following a start, the FM24C16 will expect a slave address
byte to appear on the bus. This byte consists of three parts as
shown in Figure 4.
Device Type
Identifier
Page
Select
■ Bits 7 through 4 are the device type identifier which must be
binary 1010 as shown.
1
0
1
0
A2
A1
A0
R/W
■ Bits 1 through 3 are the page select bits. They select which 256-
byte block of memory will be accessed by this operation.
Bit No.:
7
6
5
4
3
2
1
0
5
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
