typical system configuration connecting a microcontroller with an
FM24C16 and another I2C bus slave.
Pin Descriptions
SCL — Serial Clock
By convention, any device sending data onto the bus is the
transmitter, while the device that is getting the data is the receiver.
The device controlling the bus is the master and provides the clock
signal for all operations. Devices being controlled are the slaves.
The FM24C16 is always a slave device.
Transitions or states on the SDA and SCL lines denote one of
four conditions: a start, stop, data bit, or acknowledge. Figure 2
shows the signaling for these conditions, while the following four
sections describe their function.
Figure 3 shows the detailed timing specifications for the bus.
Note that all SCL specifications and the start and stop specifications
apply to both read and write operations. They are shown on one or
the other for clarity. Also, the write timing specifications apply to all
transmissions to the FM24C16, including the slave and word
address, as well as write data sent to the FM24C16 from the bus
master.
When high, the SCL clocks data into and out of the FM24C16. It
is an input only. This input is built with a Schmitt trigger to provide
increased noise immunity.
SDA — Serial Data Address
This bi-directional pin is used to transfer addresses to the
FM24C16 and data to or from the FM24C16. It is an open drain
output and intended to be wire-ORed with all other devices on the
serial bus using an external pull-up resistor. The input circuitry on
this pin is built with a Schmitt trigger to reduce noise sensitivity.
The output section incorporates slope control for the falling edges.
WP — Write Protect
If tied to V , write operations into the upper half of the
memory (bankCsCelect A set to 1 in the slave address) will be
2
disabled. Read and write operations to the lower portion of
memory will proceed normally. If the write protection feature is not
Start Condition
desired, this pin must be tied to V .
SS
A start condition is indicated to the FM24C16 when there is a
high to low transition of SDA while SCL is high. All commands to
the FM24C16 must be preceded by a start. In addition, a start
condition occurring at any point within an operation will abort that
operation and ready the FM24C16 to start a new one.
Bus Protocol
The FM24C16 employs a bi-directional two wire bus protocol
requiring a minimum of processor I/O pins. Figure 1 shows a
Figure 1. Typical System Configuration
RMIN = 1.8KΩ
R
R
RMAX = t / C
R
BUS
SCL
Bus
Master
SDA
SDA
SCL
SDA
SCL
Other
Bus Slave
FM 24C16
Figure 2. Data Transfer Protocol
SCL
SDA
7
6
0
Data Bit
(Transmitter)
Data Bit
(Transmitter)
Data Bit
(Transmitter)
Acknowledge
(Receiver)
Stop
(Master)
Start
(Master)
3
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