Figure 3. Bus Timing
Read
tRISE
tFALL
tHIGH
1/fSCL
tLOW
tSP
tSP
SCL
tSU:STA
tBUF
tAA
tDH
tSU:DAT
tHD:DAT
SDA
VALID
VALID
Start
Stop
Start
Data Bit 7
From FM24C16
Data Bit 6
From FM24C16
Data Bits 5-0
From FM24C16
Acknowledge
To FM24C16
Write
SCL
SDA
tHD:STA
tHD:DAT
tSU:STO
tSU:DAT
VALID
tAA
tDH
VALID
Start
Stop
Start
Data/Address Bit 7
To FM24C16
Data/Address Bit 6
To FM24C16
Data/Address Bits 5-0
To FM24C16
Acknowledge
From FM24C16
Notes:
All start and stop timings apply to both read and write cycles identically.
Clock specifications are the same for both read and write.
Write timing specifications apply to slave address, word address, and write data.
These timing diagrams provide representative timing relationships of the signals. They are not intended to provide functional relationships between the signals. These are provided in
Figures 5 through 9.
Read and Write Cycle AC Parameters
T = -40°C to +85°C, V = 5.0V ± 10%, Unless Otherwise Specified
A
CC
Standard Mode
Fast Mode
Symbol
Parameter
Units
Min
Max
Min
Max
400
50
f
SCL Clock Frequency
0
100
50
3
0
KHz
ns
µs
µs
µs
µs
µs
µs
ns
ns
ns
ns
µs
ns
ns
SCL
t
t
t
t
t
t
t
t
t
Noise Suppression Time Constant at SCL, SDA Inputs
SCL Low to SDA Data Out Valid
Time the Bus Must Be Free Before a New Transmission Can Start
Start Condition Hold Time
SP
0.9
AA
4.7
4.0
4.7
4.0
4.7
0
1.3
0.6
1.3
0.6
0.6
0
BUF
HD:STA
LOW
Clock Low Period
Clock High Period
HIGH
SU:STA
HD:DAT
SU:DAT
Start Condition Setup Time (for a Repeated Start Condition)
Data In Hold Time
Data In Setup Time
250
100
(3)
(5)
t
t
t
t
SDA and SCL Rise Time
1000
300
20+0.1C
300
300
RISE
b
(3)
(5)
SDA and SCL Fall Time
20+0.1C
b
FALL
Stop Condition Setup Time
4.0
0
0.6
0
SU:STO
DH
Data Out Hold Time (From SCL @ V )
IL
(3)
t
Output Fall Time (V Min to V Max)
250
20+0.1C
b
250
OF
IH
IL
(3) This parameter is periodically sampled and not 100% tested.
(5) C = Total Capacitance of One Bus Line in pF
b
4
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
