these pins are also used to specify the bit mask used during write
operations.
/CAL — Column Address Latch
0-8
These inputs are used to latch the column address and in
combination with /WE to trigger write operations. When /CAL is
high, the column address latch is transparent. When /CAL is low,
the column address latch contains the address present at the time
/CAL went low. Individual /CAL inputs are provided for each byte of
EDRAM to allow byte write capability.
A
0-10 — Multiplex Address
These inputs are used to specify the row and column
addresses of the EDRAM data. The 11-bit row address is latched on
the falling edge of /RE. The 8-bit column address can be specified
at any other time to select read data from the SRAM cache or to
specify the write column address during write cycles.
W/R — Write/Read
This input along with /F input specifies the type of DRAM
operation initiated on the low going edge of /RE. When /F is high,
W/R specifies either a write (logic high) or read operation (logic
low).
QLE — Output Latch Enable
This input enables the EDRAM output latches. When QLE is
low, the output latch is transparent. Data is latched when both /CAL
and QLE are high. This allows output data to be extended during
either static column or page mode read cycles.
/F — Refresh
This input will initiate a DRAM refresh operation using the
internal refresh counter as an address source when it is low on the
low going edge of /RE.
/HIT — Hit Pin
This output pin will be driven during /RE active read or write
cycles to indicate the hit/miss status of the cycle.
/WE — Write Enable
PD — Presence Detect
This input controls the latching of write data on the input data
pins. A write operation is initiated when both the /CAL for the
specified byte and /WE are low.
This output will indicate if the DIMM module is inserted in a
socket. When a DIMM is inserted, this pin is grounded. When no
DIMM is present, the pin is open.
/G — Output Enable
This input controls the gating of read data to the output data
pins during read operations.
V Power Supply
CC These inputs are connected to the +5 volt power supply.
V Ground
SS
/S — Chip Select
These inputs are connected to the power supply ground
connection.
This input is used to power up the I/O and clock circuitry.
When /S is high, the EDRAM remains in a powered-down condition.
Read or write cycles must not be executed when /S is high. /S must
remain low throughout any read or write operation. Only /F refresh
operation can be executed when, /S is not enabled.
DQ0-71 — Data Input/Output
These CMOS/TTL bidirectional data pins are used to read and
write data to the EDRAM. On the DM2213 write-per-bit memory,
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