Buffer Diagrams
DIMM Edge
Connector
U12A
U12D
2
3
5
48
47
45
QLE Bank0A
QLE Bank0B
QLE Bank0C
N.C.
N.C.
N.C.
QLE 8
43
42
6
44
QLE Bank0D
N.C.
9
55
54
52
/RE Bank0A
/RE Bank0B
/RE Bank0C
N.C.
N.C.
N.C.
10
12
/RE 14
49
45
13
51
/RE Bank0D
N.C.
1
58
U12B
U11A
16
17
19
2
3
5
BMO Bank0A
BMO Bank0B
BMO Bank0C
A2 Bank0A
A2 Bank0B
A2 Bank0C
15
A2 8
147
34
35
20
6
BMO Bank0D
A2 Bank0D
23
24
26
9
BE Bank0A
BE Bank0B
BE Bank0C
A4 Bank0A
A4 Bank0B
A4 Bank0C
10
12
21
A4 14
63
27
13
BE Bank0D
A4 BankOD
VDD
28
1
U12C
U11B
34
33
31
BM2 Bank0A
BM2 Bank0B
BM2 Bank0C
16
17
19
A6 Bank0A
A6 Bank0B
A6 Bank0C
36
A6 15
145
146
36
37
30
BM2 Bank0d
20
A6 Bank0D
41
40
38
BM1 Bank0A
BM1 Bank0B
BM1 Bank0C
23
24
26
A8 Bank0A
A8 Bank0B
A8 Bank0C
42
A8 21
37
BM1 Bank0D
27
A8 BankOD
VDD
29
28
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-144
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
