Buffer Diagrams
DIMM Edge
Connector
U11C
U10B
34
33
31
16
17
19
A10 Bank0A
A10 Bank0B
A10 Bank0C
/G Bank0A
/G Bank0B
/G Bank0C
A10 36
/G 15
38
31
30
20
A10 Bank0D
/G Bank0D
41
40
38
23
24
26
A9 Bank0A
A9 Bank0B
A9 Bank0C
A0 Bank0A
A0 Bank0B
A0 Bank0C
A9 42
A0 21
121
33
37
27
A9 Bank0D
A0 Bank0D
29
28
U11D
U10C
48
47
45
34
33
31
A7 Bank0A
A7 Bank0B
A7 Bank0C
A3 Bank0A
A3 Bank0B
A3 Bank0C
A7 43
A3 36
120
119
118
117
44
30
A7 Bank0D
A3 Bank0D
55
54
52
41
40
38
A5 Bank0A
A5 Bank0B
A5 Bank0C
A1 Bank0A
A1 Bank0B
A1 Bank0C
A5 49
A1 42
51
37
A5 Bank0D
A1 Bank0D
58
29
IDT74FCT162344ETPA
U10D
U10A
48
47
45
2
3
5
VDD
W/R Bank0A
W/R Bank0B
W/R Bank0C
/WE Bank0A
/WE Bank0B
/WE Bank0C
4
11
18
Vcc
Vcc
7
W/R 43
/WE 8
115
111
27
30
22
44
6
W/R Bank0D
/WE Bank0D
25
35 Vcc
50 Vcc
55
54
52
9
/F Bank0A
/F Bank0B
/F Bank0C
/S Bank0A
/S Bank0B
/S Bank0C
32
39
46
10
12
/F 49
/S 14
.22µf
51
13
/F BankOD
/S Bank0D
53
58
1
Note: Address and control buffers add a minimum of 1.5ns and a maximum of 3.8ns delay to each signal path.
2-145
RAMTRON [ RAMTRON INTERNATIONAL CORPORATION ]
