P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
timing WaVEForm oF WritE cYclE no. 1 (WE controllED)(10,11)
timing WaVEForm oF WritE cYclE no. 2 (CE controllED)(10)
ac tESt conDitionS
Input Pulse Levels
trutH taBlE
GꢀD to 3.0V
mꢈde
CE
OE
ꢂ
WE
ꢂ
i/o
Pꢈweꢉ
Standby
Active
Input Rise and Fall Times
Input Timing Reference Level
Output Timing Reference Level
Output Load
3ns
Standby
DOꢁT Disabled
Read
H
L
L
L
High Z
High Z
DOꢁT
1.5V
H
L
H
1.5V
H
Active
See Figures 1 and 2
Write
ꢂ
L
High Z
Active
ꢀotes:
10. CE and WE must be LOW for WRITE cycle.
13. Write Cycle Time is measured from the last valid address to the first
11. OE is LOW for this WRITE cycle to show tWZ and tOW
12. If CE goes HIGH simultaneously with WE HIGH, the output remains
in a high impedance state
.
transitioning address.
Document # SRAM128 REV C
Page 6
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