P4C1049/P4C1049L - HIGH SPEED 512K x 8 STATIC CMOS RAM
Data rEtEntion cHaractEriSticS (P4c1049l mꢀꢄꢀꢊꢃꢉy teꢇpeꢉꢃꢊꢂꢉe oꢆꢄy)
typ* Vcc
2.0V
=
mꢃx Vcc
2.0V
=
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
tesꢊ cꢈꢆdꢀꢊꢀꢈꢆs
mꢀꢆ
uꢆꢀꢊ
VDR VCC for Data Retention
ICCDR Data Retention Current
3.0
V
2
3
mA
ns
CE ≥ VCC -0.2V,
VIꢀ ≥ VCC -0.2V
or VIꢀ ≤ 0.2V
tCDR Chip Deselect to Data Retention Time
0
†
§
tR
Operation Recovery Time
tRC
ns
* TA = +25°C
§ tRC = Read Cycle Time
† This Parameter is guaranteed but not tested
Data rEtEntion WaVEForm
PoWEr DiSSiPation cHaractEriSticS VS. SPEED
Syꢇ Pꢃꢉꢃꢇeꢊeꢉ
teꢇpeꢉꢃꢊꢂꢉe rꢃꢆꢁe
Commercial
Industrial
-15
220
ꢀ/A
ꢀ/A
-20
185
190
200
-25
180
185
195
-35
ꢀ/A
175
185
-45
ꢀ/A
ꢀ/A
175
-55
ꢀ/A
ꢀ/A
170
-70
ꢀ/A
ꢀ/A
165
uꢆꢀꢊ
mA
mA
mA
ICC
Dynamic Operating Current*
Military
* VCC = 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V. CE = VIL, OE = VIH.
Document # SRAM128 REV C
Page 3
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