P3C1024L
ULTRA Low PoweR 128K x 8
CMoS STATiC RAM
V
CC
Current (Commercial/Industrial)
— Operating: 10mA/12mA
— CMOS Standby: 10µA/10µA
Access Times
—55/70 (Commercial or Industrial)
Single 3.3 Volts ± 0.3V Power Supply
Easy Memory Expansion Using
CE
1,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P3C1024L is a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 3.3V ± 0.3V tolerance power supply.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P3C1024L device provides asynchronous op-
eration with matching access and cycle times. Memory
locations are specified on address pins A
0
to A
16
. Reading
is accomplished by device selection (CE
1
low and CE
2
high)
and output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these conditions,
the data in the addressed memory location is presented
on the data input/output pins. The input/output pins stay
in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
The P3C1024L is packaged in a 32-pin TSOP and 445
mil SOP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document #
SRAM132
REV A
Revised February 2009