P3C1024L - ULTRA LOW POWER 128K X 8 CMOS STATIC RAM
DATA RETENTION
Symbol Parameter
Test Conditions
Min Max Unit
CE1 ≥ VCC -0.2V, CE2 ≤ 0.2V,
VIN ≥ VCC -0.2V or VIN ≤ 0.2V
VDR
VCC for Data Retention
2.0
V
(1)
ICCDR
tCDR
tR
Data Retention Current
VDR = 2.0V
10
µA
ns
Chip Deselect to Data Retention Time
Operating Recovery Time(2)
See Retention Waveform
0
100
µA
1. CE1 ≥ VDR -0.2V, CE2 ≥ VDR -0.2V or CE2 ≤ 0.2V; or CE1 ≤ 0.2V, CE2 0.2V; VIN ≥ VDR -0.2V or VIN ≤ 0.2V
LOW VCC DATA RETENTION WAVEFORM 1 (CE1 CONTROLLED)
LOW VCC DATA RETENTION WAVEFORM 2 (CE2 CONTROLLED)
Document # SRAM132 REV A
Page 7