PACE1754
TERMINAL CONNECTIONS
Case Outline: Pin Grid Array (Case Z)
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
Terminal
Number
Terminal
Symbol
B1
B2
C1
C2
D1
D2
E1
E2
F1
F2
G1
G2
H1
H2
J1
V
L5
SC
D11
D10
C11
C10
B11
A10
B10
A9
A
A
A
A
A
CC
1
0
3
4
5
6
7
IB
IB
IB
IB
IB
IB
IB
K5
SC
14
13
12
11
10
9
L6
V
CC
K6
IOR
L7
IOW
K7
MEMR
MEMW
M/IO
GND
L8
A
A
A
A
A
A
A
A
8
K8
8
9
EX RDY
L9
GND
B9
1
10
11
12
13
14
15
IB
IB
IB
IB
IB
IB
IB
IB
K9
R/W
A8
7
6
5
4
3
2
1
0
L10
K11
K10
J11
J10
H11
H10
G11
G10
F11
F10
E11
E10
RDYD
EX RDY
STRB EN
STRBD
STRBA
CPU CLK
TC
B8
A7
B7
A6
B6
GND
J2
A5
V
CC
K1
L2
K2
L3
K3
L4
K4
B5
STRT ROM
INTA
GND
SC
SC
SC
A4
3
4
B4
EX AD ER
ME PA ER
2
TIMER CLK
TEST END
RESET
A /EXT AD
0
A3
0
A /EXT AD
1
B3
PARITY/IB
16
1
A
2
A2
IB
15
TEST ON
GND
Do c um e nt # MICRO-5 REV C
Pa g e 7 o f 20
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
