AS80SSTVF16859
&
1
Truth Table
Inputs
Q outputs
RESETB
CLK
CLKB
D
Q
L
L
H
H
H
X or floating
X or floating
X or floating
↑
↑
↓
↓
H
L
H
L
2
L or H
L or H
X
Q
0
1 H = high signal level, L = low signal level, ↑ = transition low to high, ↓ = transition high to low, X = don’t care.
2 Output level before the indicated steady state input conditions were established.
Description
The 13-bit to 26-bit PC16859 is a universal bus driver designed for 2.3 V to 2.7 V V operation and SSTL_2 I/O
DD
levels, except for the LVCMOS RESETB input.
Data flow from D to Q is controlled by the differential clock (CLK/CLKB) and a control signal (RESETB). The
positive edge of CLK is used to trigger the data flow, and CLKB is used to maintain sufficient noise margins,
whereas RESETB, an LVCMOS asynchronous signal, is intended for use only at power-up. PC16859 supports
low-power standby operation. A logic level low at RESETB assures that all internal registers and outputs (Q) are
reset to the logic low state, and that all input receivers, data (D), and clock (CLK/CLKB) are switched off. Note that
RESETB must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable
during power-up.
To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESETB must be held
at a logic low level during power-up.
In the DDR DIMM application, RESETB is specified to be completely asynchronous with respect to CLK and
CLKB, therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power
standby state, the register will be cleared and the outputs will be driven to a logic low level quickly relative to the
time to disable the differential input receivers. This ensures there are no glitches on the output. When coming out
of low power standby state, however, the register will become active quickly relative to the time to enable the
differential input receivers. When the data inputs are at a logic level low and the clock is stable during the low-to-
high transition of RESETB until the input receivers are fully enabled, the design ensures that the outputs will
remain at a logic low level.
8/6/03, v.0.10
Alliance Semiconductor
P. 2 of 13
PULSECORE [ PulseCore Semiconductor ]
