AS80SSTVF16859
&
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted.)
Guaranteed by design. Not 100% tested in production
* This parameter is not necessarily production tested..
Units
VDDQ = 2.5V±0.2V VDDQ = 2.6V±0.1V
Symbol
Parameters
Min
Max
Min
Max
f
Clock frequency
200
270
MHz
ns
CLOCK
t
Pulse duration, CK, CKLB high or low
2.5
2.5
W
1
tACT
*
Differential inputs active time
22
22
22
22
ns
2
tINACT
*
Differential inputs inactive time
ns
3,5
Setup time, fast slew rate
Setup time, slow slew rate
0.75
0.9
0.4
0.6
0.4
0.6
ns
Data before CLK↑,
CLKB↓
t
S
4,5
3,5
ns
ns
Hold time, fast slew rate
0.75
0.9
Data after CLK↑,
CLKB↓
t
h
4,5
Hold time, slow slew rate
ns
1 Data inputs must be low a minimum time of tACT max, after RESETB is taken high
2 Data and clock inputs must be held at valid levels (not floating) a minimum time of tINACT max, after RESETB is taken low
3 For data signal input slew rate > 1 V/ns
4 For data signal input slew rte > 0.5 V/ns and < 1 V/ns
5 CLK, CLKB signals iput slew rates are > 1 V/ns
Switching Characteristics - DDRI / DDR333 (PC1600, PC2100, PC2700)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.5 V ± 0.2 V
Symbol
From (input)
To (output)
Min
200
1.1
1.1
–
Typ
Max
–
Units
MHz
ns
f
–
max
CLK, CLKB (TSSOP)
CLK, CLKB (VFQFN[MLF2])
RESETB
Q
Q
Q
2.8
2.8
5.0
t
PD
ns
t
–
ns
phl
Switching Characteristics - DDRI-400 (PC3200)
(Over recommended operating free-air temperature range unless otherwise noted.)
VDD = 2.6 V ± 0.1 V
Min Typ Max
Symbol
From (input)
To (output)
Units
MHz
ns
f
210
1.1
max
t
Q
Q
Q
2.2
2.48
3.5
CLK, CLKB (VFQFN[MLF2])
Simultaneous switching
PD
t
ns
PDSS
t
RESETB
ns
phl
8/6/03, v.0.10
Alliance Semiconductor
P. 8 of 13
PULSECORE [ PulseCore Semiconductor ]
