Full Frame CCD Sensor
Table 3.
Table 5. Recommended Operating Conditions
Pin #
24, 25
Signal
Ø1H, Ø2H
ØTG
Function
Typ
Tolerance
±5%
Horizontal Clocks
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
High
Low
5
0
4
-8
5
0
4
-9
2
-11
5
0
Transfer Gate Clock
Summing Gate Clock
Vertical Clock (MPP Phase)
Vertical Clocks
±10%
±5%
3, 29
ØSG
15
Ø1V (MPP)
Ø2V, Ø3V
1, 12
±5%
2, 11, 13, 30
±5%
ØLG
±5%
Lateral Charge Gate
Reset Gate
5, 23
17
8
0
3
±10%
ØRG
VOG
Output Gate
±5%
±5%
16
14
13
Amplifier Voltage Supply
Lateral Charge Drain
Amplifier Reset Drain
VDD
VLD
VRD
LS
22
4, 20
18
±5%
10
GND
GND
-2
±5%
±5%
±5%
±5%
6, 26
19
Light Shield
VSS
Video Amplifier Source
Substrate Bias
VSUB
9, 27
Table 6. Pinout Descriptions
Pin #
Sym
Function
Pin #
Sym
Function
1
2
Ø
Vertical Phase 1
Vertical Phase 3
Transfer Gate 2
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
Output Gate
1V
OG
Ø
3V
Ø
RG
Reset Gate
3
Ø
TG2
V
RD
Reset Drain
4
V
SS
Video Amplifier Source
Lateral Charge Drain
Video Output
V
LD
Lateral Charge Drain
Lateral Charge Gate 2
Light Shield
5
Ø
LG2
V
LD
6
LS
V
OUT
7
TEMP+
TEMP-
Temp+
V
DD
Video Amplifier Drain
Lateral Charge Gate 1
Horizontal Phase 2
Horizontal Phase 1
Light Shield
8
Temp-
ØLG1
Ø2H
9
V
SUB
Substrate
10
11
12
13
14
15
Ø
Transfer Gate 2
Vertical Phase 3
Vertical Phase 1
Vertical Phase 2
Transfer Gate 1
Summing Gate
Ø
TG2
1H
Ø
LS
3V
Ø
V
Substrate
1V
SUB
Ø
N/C
No Connection
Transfer Gate 1
Vertical Phase 2
2V
Ø
Ø
TG1
TG1
Ø
Ø
SG
2V
www.perkinelmer.com/opto
DSP-303.01C - 8/2002W Page 7
PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
