Full Frame CCD Sensor
Timing Requirements
(cont.)
The timing shown in Figure 4a is
repeated 1100 + 35 (or more) times
to allow the readout of one complete
line of the image.
potential which is more positive than the low state
channel potential of the transfer gate. Similar to a
lateral antiblooming drain, charge will spill prefer-
entially into the rapid discharge drain. Due to the
fixed potential barrier, the HCCD cannot be
completely cleared of charge and thus one horizontal
shift sequence is required before resumption of valid
data read.
Figure 4b shows the timing require-
ments for the vertical register. Over-
lapping of the vertical clocks are
normally longer than 5 µs. Rise and
fall times of all clocks need to be 3 µs
or longer in order to prevent spurious
charge into the CCD channel. All
vertical clock transitions should occur
when the horizontal clocks are held
steady.
Table 1. Timing Diagram Characteristics
Item
Sym
Min
Typ
Max
Units
rise/fall time
clock period
ø1, 2H
ø1, 2H
øSG
50
ns
ns
T1
T2
T3
100
Timing for MPP and normal mode is
shown. The difference between the
two modes is that during integration,
all clocks must be held low for MPP
mode.
+0
delay from
øH2 edge
ns
øSG rise/fall time
T4
T5
50
50
ns
delay from
øSG edge
øRG
+0
+0
ns
ns
ns
Array Cooling
delay from
øRG edge
øSG
T6
Both the dark current and the noise
performance of the array can be im-
proved by cooling. The dark current
will be reduced by 50% for approx-
imately every 6 - 8 ° C reduction in
array temperature. Cooling can be
T7
T8
T9
rise/fall time
øRG
øRG
ns
ns
10
pulse duration
øSG pulse duration
100
achieved via the integrated thermo-
electric cooler. The bias supplies TEC+
and TEC- electronically control this
cooler. This is a two-stage cooler
capable of reducing the temperature
of the array 40° C from the ambient
temperature. Additional cooling can be
achieved by decreasing the ambient
temperature or by cooling the heat sink
on the TE cooler as shown in Figure 6
and Figure 7.
Figure 4b. Vertical CCD Shift Register Timing and Its Relationship to
Horizontal Clocks in Normal and MPP Mode
Quiescent
Horizontal
Clear Out 1
1135 (+) ø
State of All
Horizontal
Phases
1135 (+) ø
Clock Cycles
to read 1 line
Clock Cycles
During ø
Transitions
C
ø
ø
Region of Interest
1H
2H
Rapid access to regions of interest is
facilitated by use of a lateral charge
drain. The drain is constructed adjacent
to the horizontal CCD (HCCD) shift register.
Unwanted lines of data are quickly dis-
posed without the requirement for hori-
zontal transfer. In this manner, entire lines
of image data can be disposed of by a single
vertical shift sequence, with a time penalty
of 20 µs. This is to be contrasted with the
normal read sequence which includes both
the vertical shift (20 µs), plus readout of
the 1130 horizontal elements (2260 µs).
As the unwanted lines are transferred from
storage region into the HCCD, the hori-
zontal phases are held high to maintain a
surface
ø
ø
1V
2V
Normal
Mode
ø
3V
ø
TG
End
Integration
Period
Start
Integration
Period
Repeat 330(+) Times to
Read Out the Entire Image
ø
1V
2V
3V
ø
MPP
Mode
ø
ø
TG
w w w . p e r k in e lm e r . c o m / o p t o
DSP-303.01C - 8/2002 Page 4
PERKINELMER [ PERKINELMER OPTOELECTRONICS ]
