Full Frame CCD Sensor
Summing Mode
Figure 4C. Horizontal CCD Shift Register Timing
At the end of the horizontal register, there is
an ouput summing well which can be clocked
to allow multiple-pixel summation of the
scene. This summing well is located after
the 19 extra stages of the horizontal register
and prior to the DC biased gate (VOG) as
shown in Figure 5. The summing gate (ØSG)
can be clocked with one of the horizontal
clock phases or with its own clock generator
(see Figure 4a for summing gate timing). For
example, two parallel lines of charge are
additively transferred into the serial register,
then the summing gate is pulsed low after
the charge from two serial pixels has been
transferred into the summing well. Thus,
the resulting signal represents the sum of
charges in four (2x2) contiguous pixels from
the imaging region. It effectively reduces
the 1100 x 330 device to a 550 x 165 array
and increases the pixel size by four times.
Other variations of this technique can be
useful for low-light level situations, i.e.,
scenes with low contrast or a low signal-to-
noise ratio. There is, of course, a loss in
resolution that accompanies the gain in
effective pixel size.
Normal Mode
t1
t2
t3
t4
t5
t6
t7
t8
H1
1V
2V
3V
TG
MPP Mode
t9
t10
t11
t12
t13
t14
t15
H1
1V
2V
Table
3V
TG
Table 2. Vertical Timing Diagram Characteristics
Item
Sym
Min
Typ
Max
Units
FE H1 to FE 1V
FE 1V to RE 3V
RE 3V to FE 2V
FE 2V to RE 1V
RE 1V to FE 3V
FE 3V to RE 2V
RE 2V to FE TG
FE TG to RE H1
FE H1 to RE 2V
RE 2V to RE 3V
RE 3V to FE 2V
FE 2V to RE 1V
RE 1V to FE 3V
FE 3V to FE TG
FE TG to RE H1
2.6
2.6
2.6
5.2
1.4
1.4
4.6
2.6
2.6
5.2
2.6
2.6
2.8
4.6
2.6
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
t1
Output Amplifier
t2
t3
t4
There is an on-chip amplifier that is
located at the end of the extended shift
register. The amplifier is a two stage
buried channel transistor amplifier as
shown in Figure 5. It is designed to operate
with data rates in excess of 10 MHz. It
has a bandwidth of approximately 60 MHz
with a 10 pF load.
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t14
Temperature Monitoring
The RA1133J device has a temperature
sensor integrated into the package for
monitoring array temperature.
Figure 4a. Horizontal CCD Shift Register Timing
Timing Requirements
t1
t2
The timing recommended to run the RA1133J
imager in the low speed and low noise mode of
operation is shown in Figures 4A, 4B, and 4C. A
50% duty cycyle, two phase clock will drive the
horizontal register to its highest speed. Figure 4a
shows the timing of the horizontal two phase
clocks, summing well clock and reset clock. To
achieve high charge transfer, serial clocks must
cross between 10% and 90% of the peak voltage.
In addition, the rise and fall times of the two
phase clocks need to be more than 50 ns in order
to prevent the injection of spurious charge into
the CCD channel.
Ø1H
Ø2H
t4
t3
t9
ØSG
t5
t7
t6
t8
ØRS
Video
Output
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DSP-303.01C - 8/2002W Page 3
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