Oxford Semiconductor Ltd.
OXFW970 Data Sheet
Table 5 OXFW970 Pin Allocations (Sheet 2 of 2)
(1)
Pin
No.
Bits
Name
Description
Type
15
JTAG_UART_SEL
Selects UART mode:
Low—UART
Power & Ground
2,11,16,38,63,88
6
9
VDD1V8
VDD3V3
3,22,30,46,50,71,83,
97,99
10,17,39,64,87
5
8
VSS1V8
VSS3V3
9,23,31,47,56,72,
82,96
NC
1,7,8,12,13,14,78,80,
86,94,95
11
14
NC
51,52,53,54,55,57,58,
67,69,70,73,74,75,79
Reserved
Tie low using 4K7 Ω resistor (typical)
Note:
1
Type key: format is [(W_)X(Y)(_Z(A))] where the following conventions apply:
W—Tolerance
X—Type
Input
Y—Pull
Z—Drive
4 mA
T—Tristate
Tristate
Normal
5
5 V
I
U
D
Pull up
4
8
T
3V3
O
B
Output
Pull down
None
8 mA
Bidirectional
12
12 mA
Figure 3 on page 8 shows the OXFW970 package.
DS-0004 Jun 05 (2)
External—Free Release
7
OXFORD [ OXFORD SEMICONDUCTOR ]
