OXFW970 Data Sheet
Oxford Semiconductor Ltd.
Table 5 OXFW970 Pin Allocations (Sheet 1 of 2)
Pin
No.
Bits
8
2
1
1
1
1
1
1
1
1
1
1
4
1
1
8
Type
Name
Description
LINK (External Interface) (16 pins)
26,27,28,29,32,33,34,
35
36,37
41
42
43
45
40
44
AUDIO
85
84
49
68
76,77,81,48
65
66
GPIO (8 pins)
62,61,60,59,18,19,20,
21
PLL (5 pins)
91
93
92
90
89
100
4
5
6
MISC
24
25
98
1
1
1
5_IU
5_I
5_ID
Z_FORCE_FLASH
Z_RESET
SEL_B_PHY
Allows flash memory programming
Main asynchronous reset
Selects between 1394a & 1394b mode:
High—B PHY
Low—A PHY
1
1
1
1
1
1
1
1
1
P
P
P
P
P
O_4
5_BU_4T
5_IU
5_IU
PLL_DVDD
PLL_DVSS
PLL_AVDD
PLL_AVSS
VBB_PLL
UART_SOUT
UART_Z_RTS
UART_SIN
UART_Z_CTS
PLL digital 1.8V
PLL digital GND
PLL analogue 1.8 V
PLL analogue GND
PLL bulk bias
UART transmitter serial data output
Active-low request-to-send output
Receiver serial data input
Active-low clear-to-send input.
5_B_4T
GPIO[7:0]
General purpose I/O pins
5_O_4
5_I
5_BD_4T
5_B_4T
5_B_4T
5_B_4T
5_B_4T
256FS_CLK_O
256FS_CLK_I
BIT_CLK
WORD_CLK
AUDIO_DATA[3:0]
SYS_FS_PDOUT
VCO_FS_PDOUT
Sys clock generated 256Fs clock (to DAC)
Returned (smoothed) 256Fs clock (from VCO)
Serial audio bit clock
Serial audio word clock
Audio data synchronised to BIT_CLK
Output-of-audio phase detector from SYS_CLK
Output-of-audio phase detector from VCO clock
5_BD_4T
5_BD_4T
5_IU
O_4
5_IU
O_4
O_8
5_IU
PD[7:0]
CTL[1:0]
PCLK
LREQ
LINKON
LPS
LCLK
PINT
PHY-link data bus
PHY-link control bus
49.152-/ 98.304-MHz clock sourced by PHY. Drives
main clock system
Link request
Requests link to power up when in a low power mode
Indicates to PHY that link is powered and ready
B only—PCLK returned to PHY
B only—PHY Interrupt
UART / JTAG (4 pins) mode defined by JTAG_UART_SEL pin
6
External—Free Release
DS-0004 Jun 05 (2)
OXFORD [ OXFORD SEMICONDUCTOR ]
