FEDL87V2107-01
OKI Semiconductor
ML87V2107
2.1.9 Direct Noise Reduction Output Mode
This IC can directly retrieve data that has been processed by the noise reduction function from the output port
without intervention of the field memory by setting the external pin DNR = 1 or internal register IDNR
(SUB:48h-bit[7]) = 1,
In this case, the output data is output from the output pin (YO[7:0], CO[7:0]) for the input after a delay of 19 clock
cycles (16-bit mode) or 40 clock cycles (input 8 bits, ITU-R BT.656 mode) under the internal input clock ICLK.
The Sync. signals input to IVS and IHS are also output from the OVS and OHS pins after the same delay period.
Normally, this IC supports the YCbCr16bit mode only as the output format; however, in YCbCr8bit mode, and
ITU-R BT.656 mode, data can be output in the same 8-bit format as the input format by setting DOSEL
(SUB:60h-bit[1]) = 1. In this case, in ITU-R BT.656 mode, the same data as the input data are output to SAV and
EAV.
AxICLK
IVS
OVS
AxICLK
IHS
OHS
AxICLK
YI
CI
Valid data
YO
CO
Valid data
HREF
A = 19 (16-bit mode), 40 (8 bits, ITU-R BT.656 mode)
Figure F2-1-9(2) Direct Noise Reduction Output Mode Input/Output Timing
• Function restriction in direct noise reduction output mode
When a direct noise reduction output mode is selected, the functions of this IC are restricted, disabling 2DLPF,
asynchronous output, and Sync. signal generation functions. Set also OCLK = ICLK.
For the register setting, only the following registers that are directly related to input control can be changed. If the
setting of any other registers is changed, an operation error occurs.
Registers that can be changed
sub-40h to sub-45h, sub-48h to 59h, sub-60h(bit[7:5],bit[2:1])
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