ESMT
M12L16161A
AC OPERATING TEST CONDITIONS (VDD=3.3V ± 0.3V,TA= 0 to 70°C )
Parameter
Value
2.4 / 0.4
1.4
tr / tf = 1 / 1
1.4
See Fig.2
Unit
V
V
ns
V
Input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
3.3V
Vtt =1.4V
1200 Ω
50
Ω
Output
VOH(DC) = 2.4V, IOH = -2mA
VOL(DC) = 0.4V, IOL = 2mA
Output
Z0=50 Ω
30 pF
870 Ω
30 pF
(Fig.2) AC Output Load Circuit
(Fig.1) DC Output Load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Version
Parameter
Symbol
Unit
Note
-5
-7
Row active to row active delay
tRRD(min)
tRCD(min)
10
14
20
ns
ns
1
1
15
RAS to CAS delay
Row precharge time
tRP(min)
tRAS(min)
15
40
20
42
ns
ns
1
1
Row active time
tRAS(max)
tRC(min)
100
us
Row cycle time
55
63
ns
1
2
2
2
3
Last data in to new col. Address delay
Last data in to row precharge
Last data in to burst stop
tCDL(min)
1
2
1
1
2
1
CLK
CLK
CLK
CLK
tRDL(min)
tBDL(min)
Col. Address to col. Address delay
tCCD(min)
CAS latency=3
CAS latency=2
Number of valid output data
ea
4
Note: 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and
then rounding off to the next higher integer.
2.
Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
The earliest a precharge command can be issued after a Read command without the loss of data is CL+BL-2 clocks.
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2005
Revision : 2.4 6/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
