ESMT
M12L16161A
DC CHARACTERISTICS
°C
(Recommended operating condition unless otherwise noted, TA = 0 to 70
VIH(min)/VIL(max)=2.0V/0.8V)
CAS
Latency
Version
Parameter
Symbol
Test Condition
Unit Note
-5
-7
Burst Length = 1
tRC ≥ tRC (min), tCC ≥ tCC (min), IOL= 0mA
Operating Current
(One Bank Active)
ICC1
130
100
mA
mA
1
Precharge Standby
Current in power-down
mode
ICC2P
2
2
CKE ≤ VIL(max), tCC =15ns
ICC2PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC =15ns
25
10
mA
ICC2N
Precharge Standby
Current in non
power-down mode
Input signals are changed one time during 30ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable
mA
mA
ICC2NS
ICC3P
10
10
CKE ≤ VIL(max), tCC =15ns
Active Standby Current
in power-down mode
ICC3PS
CKE ≤ VIL(max), CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns
25
10
mA
ICC3N
Active Standby Current
in non power-down
mode
Input signals are changed one time during 30ns
CKE ≥ VIH (min), CLK ≤ VIL(max), tCC= ∞
Input signals are stable
mA
mA
ICC3NS
(One Bank Active)
IOL= 0Ma, Page Burst
3
1
2
150
150
150
120
120
120
Operating Current
(Burst Mode)
ICC4
All Band Activated, tCCD = tCCD (min)
2
Refresh Current
ICC5
ICC6
tRC ≥ tRC(min)
CKE ≤ 0.2V
mA
mA
Self Refresh Current
1
Note: 1.Measured with outputs open. Addresses are changed only one time during tCC(min).
2.Refresh period is 32ms. Addresses are changed only one time during tCC(min).
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2005
Revision : 2.4 5/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
