ESMT
M12L16161A
Mode Register
11
0
11
x
10
0
10
x
9
0
9
1
8
0
8
0
7
1
7
0
6
6
5
5
4
4
3
3
2
2
1
1
0
0
JEDEC Standard Test Set (refresh counter test)
LTMODE
WT
BL
Burst Read and Single Write (for Write
Through Cache)
11
10
9
9
x
9
8
1
8
1
8
0
7
0
7
1
7
0
6
6
v
6
5
5
v
5
4
4
v
4
3
3
v
3
2
2
v
2
1
1
v
1
0
Use in future
11
x
11
0
10
x
10
0
0
v
0
Vender Specific
v =Valid
0
LTMODE
WT
BL
Mode Register Set
x =Don’t care
Bit2-0
000
001
010
011
100
101
110
111
WT=0
1
2
4
8
R
R
R
WT=1
1
2
4
8
R
R
R
R
Burst length
Full page
0
1
Sequential
Interleave
Wrap type
Bits6-4
CAS Latency
000
001
010
011
100
101
110
111
R
R
2
Latency mode
3
R
R
R
R
Mode Register Write Timing
Remark R : Reserved
CLOCK
CKE
CS
RAS
CAS
WE
A0-A11
Mode Register Write
Elite Semiconductor Memory Technology Inc.
Publication Date : May. 2005
Revision : 2.4 9/30
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
