EliteMT
M11L416256SA
(Continued)
-35
PARAMETER
SYMBOL
UNIT
NOTES
MIN
0
MAX
tRCH
tRRH
tCLZ
ns
ns
ns
9,15,19
Read Command Hold Time Reference to CAS
Read Command Hold Time Reference to RAS
CAS to Output in Low-Z
9
0
20
3
Output Buffer Turn-off Delay From CAS or
RAS
tOFF1
ns
ns
3
15
8
10,17,20
17,26
tOFF2
Output Buffer Turn-off to OE
tWCS
tWCH
Write Command Setup Time
Write Command Hold Time
ns
ns
11,15,18
15,25
0
5
tWCR
tWP
ns
ns
ns
15
15
15
30
5
Write Command Hold Time(Reference to RAS )
Write Command Pulse Width
tRWL
9
Write Command to RAS Lead Time
tCWL
ns
15,19
7
Write Command to CAS Lead Time
Data-in Setup Time
tDS
tDH
ns
ns
12,20
12,20
0
5
Data-in Hold Time
tDHR
tRWD
tAWD
tCWD
ns
ns
ns
ns
30
51
34
26
2.5
Data-in Hold Time (Reference to RAS )
RAS to WE Delay Time
11
11
Column Address to WE Delay Time
11,18
2,3
CAS to WE Delay Time
Transition Time (rise or fall)
Refresh Period (512 cycles)
tT
ns
50
8
tREF
ms
tRPC
tCSR
tCHR
ns
ns
ns
10
10
10
RAS to CAS Precharge Time
CAS Setup Time(CBR REFRESH)
CAS Hold Time(CBR REFRESH)
1,18
1,19
OE Hold Time From WE During
Read-Mode-Write Cycle
tOEH
ns
16
4
tOES
tOEHC
tOEP
ns
ns
ns
4
2
2
OE Low to CAS High Setup Time
OE High Hold Time From CAS High
OE Precharge Time
OE Setup Prior to RAS During Hidden
Refresh Cycle
tORD
ns
ns
0
5
Last CAS Going Low to First CAS
Returning High
tCLCH
21
tCOH
tWHZ
tRASS
tRPS
ns
ns
3
3
Data Output Hold After CAS Returning Low
Output Disable Delay From WE
7
μ s
27,28
27,28
27,28
100
65
-50
Self Refresh RAS Low Pulse width
Self Refresh RAS High Precharge Time
Self Refresh CAS Hold Time
ns
ns
tCHS
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4 5/16
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
