EliteMT
M11L416256SA
CAPACITANCE (Ta = 25 °C , VCC = 3.3V ± 10%)
PARAMETER
SYMBOL
CI1
TYP
MAX
5
UNIT
pF
Input Capacitance (address)
-
-
-
Input Capacitance (RAS , CASH, CASL , WE , OE )
CI2
7
pF
Output capacitance (I/O0~I/O15)
CI / O
10
pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =3.3V ± 10%, VSS = 0V) (note 14)
Test Conditions
Input timing reference levels : 0.8V, 2.0V
Output reference level : VOL= 0.8V, VOH=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed tT = 2ns
-35
PARAMETER
SYMBOL
UNIT
NOTES
MIN
65
MAX
Read or Write Cycle Time
Read Write Cycle Time
tRC
ns
ns
tRWC
95
EDO-Page-Mode Read or Write Cycle
Time
tPC
14
42
ns
ns
22
22
EDO-Page-Mode Read-Write Cycle
Time
tPCM
tRAC
tCAC
35
10
10
18
20
ns
ns
ns
ns
ns
ns
ns
4
Access Time From RAS
Access Time From CAS
5,20
13,20
tOAC
tAA
Access Time From OE
Access Time From Column Address
tACP
20
25
Access Time From CAS Precharge
RAS Pulse Width
tRAS
tRASC
tRSH
tRP
35
35
10
25
5
10K
100K
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
ns
ns
ns
ns
ns
ns
RAS Precharge Time
CAS Pulse Width
tCAS
tCSH
tCP
24
19
10K
25
30
5
CAS Hold Time
CAS Precharge Time
RAS to CAS Delay Time
6,23
7,18
19
tRCD
tCRP
10
5
0
5
8
0
5
ns
ns
ns
ns
ns
ns
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
tASR
tRAH
tRAD
17
8
RAS to Column Address Delay Time
Column Address Setup Time
Column Address Hold Time
Column Address Hold Time (Reference
to RAS )
tASC
tCAH
18
18
tAR
30
ns
ns
tRAL
tRCS
18
0
Column Address to RAS Lead Time
Read Command Setup Time
15,18
Elite Memory Technology Inc
Publication Date: Aug. 2005
Revision : 1.4
4/16