EliteMT
TRUTH TABLE
FUNCTION
M11B416256A
ADDRESSES
DQS
NOTES
RAS
CASL CASH
OE
WE
ROW
X
COL
X
Standby
H
L
L
L
L
HꢁX HꢁX
X
H
H
H
L
X
L
L
L
X
High-Z
Read : Word
L
L
L
H
L
ROW
ROW
ROW
ROW
COL
COL
COL
COL
Data-Out
Read : Lower Byte
Read : Upper Byte
Write : Word (Early Write)
Lower Byte, Data-Out
Upper Byte, Data-Out
H
L
L
Data-In
Lower Byte, Data-In ,
Upper Byte, High-Z
Write : Lower Byte (Early)
Write : Upper Byte (Early)
L
L
L
H
L
L
X
X
ROW
ROW
COL
COL
Lower Byte, High-Z ,
Upper Byte, Data-In
H
L
L
L
Read-Write
1st Cycle
EDO-Page-Mode
2nd Cycle
Read
L
HꢁL LꢁH ROW
COL
COL
COL
Data-Out, Data-In
Data-Out
1, 2
2
L
HꢁL HꢁL
HꢁL HꢁL
LꢁH LꢁH
HꢁL HꢁL
HꢁL HꢁL
H
H
H
L
L
L
L
X
X
ROW
ROW
L
Data-Out
2
Any Cycle
L
Data-Out
2
1st Cycle
L
COL
COL
COL
COL
COL
Data-In
1
EDO-Page-Mode
Write
2nd Cycle
L
L
Data-In
1
1st Cycle
L
L
HꢁL HꢁL HꢁL LꢁH ROW
HꢁL HꢁL HꢁL LꢁH
Data-Out, Data-In
Data-Out, Data-In
Data-Out
1, 2
1, 2
2
EDO-Page-Mode
Read-Write
2nd Cycle
Hidden Refresh
LꢁHꢁL
L
H
L
L
H
L
H
X
H
L
X
X
ROW
ROW
X
L
High-Z
High-Z
RAS -Only Refresh
CBR Refresh
HꢁL
X
3
*Note : 1. These WRITE cycles may also be BYTE WRITE cycles (either CASL or CASHactive).
2. These READ cycles may also be BYTE READ cycles (either CASL or CASH active).
3. Only one CAS must be active ( CASL or CASH).
Elite Memory Technology Inc
Publication Date : Jun. 2006
Revision : 2.1 7/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
