EliteMT
M11B416256A
CAPACITANCE (Ta = 25 °C , VCC = 5V ± 10%)
PARAMETER
SYMBOL
CI1
TYP
MAX
5
UNIT
pF
Input Capacitance (address)
-
-
-
Input Capacitance (RAS , CASH, CASL , WE , OE )
CI2
7
pF
Output capacitance (I/O0~I/O15)
CI / O
10
pF
AC ELECTRICAL CHARACTERISTICS (Ta = 0 to 70 °C , VCC =5V ± 10%, VSS = 0V) (note 14)
Test Conditions
Input timing reference levels : 0V, 3V
Output reference level : VOL= 0.8V, VOH=2.0V
Output Load : 2TTL gate + CL (50pF)
Assumed tT = 2ns
-25
-35
PARAMETER
SYMBOL
UNIT Notes
MIN
43
MAX
MIN
65
MAX
Read or Write Cycle Time
tRC
tRWC
tPC
ns
ns
Read Write Cycle Time
65
95
EDO-Page-Mode Read or Write Cycle Time
EDO-Page-Mode Read-Write Cycle Time
Access Time From RAS
10
14
ns
ns
ns
ns
22
22
tPCM
tRAC
tCAC
32
42
25
35
4
8
8
10
10
18
20
5,20
Access Time From CAS
tOAC
tAA
ns 13,20
ns
Access Time From OE
Access Time From Column Address
12
tACP
14
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
25
Access Time From CAS Precharge
RAS Pulse Width
tRAS
tRASC
tRSH
tRP
25
25
8
10K
100K
35
10K
RAS Pulse Width (EDO Page Mode)
RAS Hold Time
35
10
25
100K
15
4
RAS Precharge Time
CAS Pulse Width
tCAS
tCSH
tCP
10K
17
24
19
5
30
5
10K
25
21
4
CAS Hold Time
CAS Precharge Time
RAS to CAS Delay Time
6,23
7,18
19
tRCD
tCRP
10
10
5
0
5
8
5
0
5
8
ns
ns
ns
ns
CAS to RAS Precharge Time
Row Address Setup Time
Row Address Hold Time
tASR
tRAH
tRAD
tASC
tCAH
13
17
8
RAS to Column Address Delay Time
Column Address Setup Time
0
5
0
5
ns
ns
18
18
Column Address Hold Time
Column Address Hold Time (Reference to
RAS )
tAR
22
12
30
18
ns
ns
tRAL
Column Address to RAS Lead Time
Elite Memory Technology Inc
Publication Date : Jun. 2006
Revision : 2.1 4/15
ESMT [ ELITE SEMICONDUCTOR MEMORY TECHNOLOGY INC. ]
