PBL 402 15
Maximum Ratings
Parameter
Condition
Symbol
Min.
Typ.
Max.
Unit
Supply voltage
Voltage applied between two different
supply pins, except VccRF (a)
Vcc
Vccdiff
5.5
0.6
V
V
Voltage applied between two
different ground pins (a)
Maximum input power
Maximum power dissipation
IC storage temperature
Lead temperature
Grounds are clamped together
by diodes
LNA input
Gnddiff
0.6
V
Pmax
PD
TS
10
dBm
mW
°C
250
150
300
-65
solder, 10 sec.
TLEAD
°C
(a). Under continous operation and during power-up sequences.
Handling
Every pin withstands the ESD test in accordance with MIL-STD-883 (method 3050) and IEC 68-2.
CAP
IFIN
IFOUT
π/4
π/4
PIN switch
÷2
÷2
+
+
RXIN
IF Filt
-π/4
-π/4
RSSI
RSSI
IR RX
IR IF
TX
TXOUT
PA-GATE
FM Demod
GATE
Slave PLL
÷2
+
×2
Slice
control
PLL
Modulator
DTX
Control
ƒ-φ
÷R
LD
LD
DRX
D
ST EN
CK
RXEN TXEN
SHOLD
DSL
VTUNE
MOD
CP
REF
Figure 6. Block diagram.
7