PBL 402 15
48 47 46 45 44 43 42 41 40
37
39 38
1
2
36
EN
REF
GndRF
RX+
35
3
VccPLL
GndPLL
GndCP
34
33
32
31
30
29
28
27
26
25
RX-
4
GndRF
IFOUT+
IFOUT-
LD
5
6
CP
7
VccCP
8
NC
NC
VccIF
GndIF
IFIN+
IFIN-
9
10
11
12
VccVCO
VTUNE
GndVCO
PA Gate
13 14 15
17
19 20
18 21 22 23 24
16
Figure 5. Pinning configuration.
Pin Descriptions:
Refer to pin configuration.
Pin number
Name
Function
Schematic in/output of the pin
VCCPLL
165 k
1
EN
Enable 3-wire interface and synthesiser.
EN
GndPLL
V
CCPLL
2
REF
PLL reference clock input
REF
GndPLL
Clamp to GndPLL
3
4
5
VCCPLL
GndPLL
GndCP
Voltage supply to the frequency synthesiser.
Ground connection to the frequency synthesiser.
Ground connection to the charge pump.
A diode to GndCP and GndRF
A diode to GndPLL and GndVCO
VCCCP
6
7
CP
Charge pump output.
CP
GndCP
Clamp to GndCP
VCCCP
Voltage supply to the charge pump.
3
ERICSSON [ ERICSSON ]
