C9834
Low EMI Clock Generator for Intel 810 Chipset / Pentium II and Pentium III Systems
Preliminary
2-Wire I2C Control Interface (Cont.)
Byte 4: Sel Clock Register (1 = select high, 0 = select low)
Bit
7
6
5
4
@Pup
Pin#
Pin Description
S3
S2
S1
0
0
0
0
0
-
-
-
-
-
S0
3
0 = Hardware Frequency Selection
from external jumpers,
1= Software Frequency selection
from bits1,4,5,6,7
Spread Enable(1)/ disable(0)
S4
2
1
0
0
0
0
-
-
-
Reserved
Byte 5: Control Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@Pup
Pin#
Pin Description
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ACK
ACK
SDATA IS OUTPUT PIN
COMMAND BYTE
(DON'TCARE)
1
1
0
1
0
0
1
0
SDATA IS INPUT PIN
SDATA
MSB
LSB
SCLK
8
START CONDITION
CONTINUED
ACK
ACK
ACK
COUNT BYTE
(DON'TCARE)
BYTE 0
(VALID DATA)
BYTE N (LAST
VALID DATA)
CONTINUED
8
8
8
STOP CONDITION
I2C Communications Waveforms. Fig. 6
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev. 1.1
9/7/1999
Page 6 of 15
CYPRESS [ CYPRESS ]
