C9834
Low EMI Clock Generator for Intel 810 Chipset / Pentium II and Pentium III Systems
Preliminary
Pin Description
PIN No.
Pin Name
PWR
VDD
TYPE
PU
Description
S3 / HDREF
1
This is a bi-directional pin. See page 3 for input strapping. When this pin is
an input, it functions as part of the frequency selection address,S3 (see
Table 1,p1). When it is an output, it is HDREF a high drive buffered output
of the signal applied at Xin
XIN
XOUT
3V66 (0,1)
S0 / PCI0
S1 / PCI1
S2 / PCI2
3
4
7, 8
VDD
VDD
VDD
OSC1
OSC1
14.318 MHz Crystal input. See Crystal Spec. page 11.
14.318 MHz Crystal output
3.3 V AGP clock outputs, Synchronous to CPU clocks, see table 1 page1.
These are bi-directional pins. See Application Note,p.3, for input strapping.
When they are in input mode, they function as the frequency selectors
S0,S1,S2 (see Table 1,p1). When they are in output mode, they function
as PCI(0:2) clock outputs, and they are synchronous to the CPU clocks.
3.3 V PCI clock outputs, they are synchronous to CPU clocks. See page 9
for timing.
These are fixed 48MHz outputs for USB and HUB clocks.
This is a bi-directional pin. See Application Note,p.3, for input strapping.
When this pin is an input, it functions as a SIO select pin for selecting the
clock frequency at this same pin.
10, 11, 12
PU
PD
PU
PCI (3:7)
14, 15, 17,
18, 19
21, 22
23
VDD
VDD
48MHz-(0:1)
24M_48MHz / SIO
PU
PU
If SIO is strapped high, then output = 24 MHz.
If SIO is strapped low, then output = 48MHz.
SDATA
25
Serial data input pin. Conforms to the Philips I²C specification of a Slave
Receiver device. This pin is an input when receiving data. It is an open
drain output when acknowledging. See I²C function description,p.5.
Serial clock input pin. Conforms to the Philips I²C 100KHz Specs.
When this input pin is asserted low, the device is in Power Down mode; all
outputs are held low, and internal PLL’s are shutoff.(see p.4)
2.5V clock output synchronous to the CPU clocks. See Table 1, p1.
3.3V High Speed SDRAM outputs. They are synchronous to CPU.
SCLK
PD#
28
29
VDD
VDD
PU
PU
IOAPIC
SDRAM (0:7,_F)
47
VDD
VDD
31, 32, 33,
35, 36, 37,
39, 40, 41
44, 45
34, 42
46
CPU(0,1)
VDDS
VDDCPU
VDDI
VDD
2.5 V Host bus clock outputs. They are powered by VDDCPU.
3.3 V Power Supply for SDRAM
2.5V Power Supply pin for CPU(0:1)
2.5V Power Supply pin for IOAPIC
Common Ground pins.
-
-
-
-
48
VSS
5,9,13,20,26,
30,38, 43
2,6,16,24,27
-
VDD
-
3.3 V Common Power Supply pins.
Table 2
PU: This denotation refers to an internal pull up of 250kΩ Typical. (applies to signals: S3, S2, S0, SIO, and PD#)
PD: This denotation refers to an internal down up of 250kΩ Typical. (applies to signal: S1)
S4: is an internal signal with a pull-down. It will therefore, default to a ‘0’ after powerup. This signal may only be programmed
through I²C, Byte4, Bit1.
A bypass capacitor (0.1µF) should be placed as close as possible to each positive power pin (<0.2”). If these bypass
capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductances of
the traces.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev. 1.1
9/7/1999
Page 2 of 15
CYPRESS [ CYPRESS ]
