C9834
Low EMI Clock Generator for Intel 810 Chipset / Pentium II and Pentium III Systems
Preliminary
Power Management
Power Management on this device is controlled by a single pin, PD# (pin29). When PD# is high (default) the device is
in running and all signals are active.
When PD# is asserted (forced) low, the device is in shutdown (or in power down). When in power down, all outputs are
synchronously stopped in a low state (see fig.5 below), all PLL’s are shut, and the crystal oscillator is disabled. When
the device is shutdown the I2C function is also disabled.
Power Management Timing
W ait C y c les
W ait 300uS Min
PD#
P
1
2
CPU @ 100MHz
SDRA M @ 100MHz
3V66 at 66.6MHz
PCI at 33.3MHz
P
P
P
P
P
P
IOA PIC at 16.67MHz
48MHz
Figure 5
Current Consumption
Signal
Maximum 2.5 Volt Current
Consumption (VDD2.5 =2.625)
Maximum 3.3 Volt Current Consumption
(VDD3.3 = 3.465 V)
PD# = Logic Low
100 A
70 mA
1 mA
66.8 MHz (PD# = 1, S3=1, S2=1,
S1=0, S0=0)
280 mA
100.2 MHz (PD# = 1, S3=1, S2=1,
S1=1, S0=0)
100 mA
280 mA
Table 2
When exiting the power down mode, the designer must supply power to the VDD pins first, a minimum of 200mS before
releasing the PD# pin high.
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev. 1.1
9/7/1999
Page 4 of 15
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