C9834
Low EMI Clock Generator for Intel 810 Chipset / Pentium II and Pentium III Systems
Preliminary
Power on Bidirectional Pins
Power Up Condition:
Pins 1, 11, 12, 13, and 23 are Power up bi-directional pins and are used for selecting different functions in this device
(see Pin description, Page 2). During power-up of the device, these pins are in input mode (see Fig 3, below), therefore,
they are considered input select pins internal to the IC. After a settling time, the Selection data is latch into internal
control registers and these pins become toggling clock outputs.
VDD RAIL
POWER SUPPLY
RAMP
PCI(0:2) / S(0:2)
HDREF /S3
-
Hi-Z INPUTS
TOGGLE OUTPUTS
24M_48M / SIO
SELECT DATA IS LATCHED INTO REGISTER THEN PIN BECOMES CLOCK OUTPUT SIGNAL
Fig. 3
Strapping Resistor Options:
Vdd
The power up bidirectional pins have internal pullup
(pins 1, 10, 12, 23, 25, 28, and 29) or pulldown (pin 11)
resistors connected to them internally. These resistors
insure that if these input pins are not connected through
an external resistor to Vdd or Vss at power up that they
will load the default values into the device’s internal
resisters. If the Vdd power supply ramps from 0 to Vdd
is more than 3 ms at power up, it is recommended that
an external 50K resistor be added to this internal device
to guarantee that the device will correctly sense these
programming selections. In this case, the designer may
choose one of two configurations, see Fig. 4A and Fig.
4B.
Rup
10K
IMI C9834
Rd
Load
Bidirectional
JP1
JUMPER
Fig.4A
Rdn
10K
Fig. 4A represents an additional pull up resistor 10KΩ
connected from the pin to the power line, which allows
a faster pull to a high level. If a selection “0” is desired,
then a jumper is placed on JP1 to a 10KΩ resistor as
implemented as shown in Fig.4A. Please note the
selection resistors (Rup, and Rdn) are placed before
the Damping resistor (Rd) close to the pin.
JP2
3 Way Jumper
Vdd
3
1
2
Rsel
10K
IMI C9834
Rd
Fig. 4B represent a single resistor 10KΩ connected to a
3 way jumper, JP2. When a “1” selection is desired, a
jumper is placed between leads1 and 3. When a “0”
selection is desired, a jumper is placed between leads
1 and 2.
Load
Bidirectional
Fig.4B
INTERNATIONAL MICROCIRCUITS, INC. 525 LOS COCHES ST.
MILPITAS, CA 95035 TEL 408-263-6300, FAX 408-263-6571
http://www.imicorp.com
Rev. 1.1
9/7/1999
Page 3 of 15
CYPRESS [ CYPRESS ]
