PRELIMINARY
B9852
High Performance Pentium III Clock Buffer
Byte 3: Active/Inactive Register
Serial Control Registers (Cont.)
Bit
7
6
5
4
3
2
1
0
Name
Pin#
@ Pup Description
Byte 0: Active/Inactive Register (1 = enable, 0 =
Stopped Low)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
x
x
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Reserved (Intel)
Bit
7
6
5
4
3
2
1
0
Name
PCI1
PCI2
PCI3
PCI4
PCI5
PCI6
PCI7
PCI8
Pin # @ Pup Description
6
1
1
1
1
1
1
1
1
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
7
10
11
14
15
17
18
Byte 4: Active/Inactive Register
Bit
7
6
5
4
3
2
1
0
Name
Pin#
@ Pup Description
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
x
x
x
x
x
x
x
1
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
1=normal, 0=test mode
Byte 1: Active/Inactive Register (1 = enable, 0 =
Stopped Low)
Bit
7
6
5
4
3
2
1
0
Name
PCI9
Pin#
21
22
24
25
36
37
54
55
@ Pup Description
1
1
1
1
1
1
1
1
1=Active, 0=Inactive
PCI10
PCI11
PCI12
48 MHz_2
48 MHz_1
Ref2
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
Notes:
Inactive means outputs are held LOW and are disabled
from switching. These outputs are designed to be
configured at power-on and are not expected to be
configured during the normal modes of operations.
Ref1
Byte 2: Active/Inactive Register (1 = enable, 0 =
Stopped Low)
The “@ Power Up” (@Pup) column defines the state of
the bits in these registers immediately after the device
has been powered up. X is a “don’t care” condition.
Bit
7
6
5
4
3
2
1
0
Name
3V66_6
3V66_5
3V66_4
3V66_3
3V66_2
3V66_1
-
Pin#
42
43
46
47
50
51
-
@ Pup Description
1
1
1
1
1
1
x
x
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
1=Active, 0=Inactive
Reserved (Intel)
When “test mode” is enabled (Byte 4 Bit 0 is set true
(logic low) state, the 48MHz output clocks become
7.159 MHz (REF/2) clocks. These clocks are then
defined from the REF clock (14.318MHz in).
-
-
Reserved (Intel)
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07076 Rev. **
5/9/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Page 7 of 13
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