PRELIMINARY
B9852
High Performance Pentium III Clock Buffer
Maximum Ratings
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Maximum Input Voltage Relative to VSS: VSS - 0.3V
Maximum Input Voltage Relative to VDD: VDD + 0.3V
Storage Temperature:
Operating Temperature:
Maximum ESD protection
Maximum Power Supply:
-65ºC to + 150ºC
0ºC to +85ºC
2000V
5.5V
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters (VDD = VDDN = VDDP = VDDU = VDDL = VDDR = 3.3V ±5%, , TA = 0ºC to +85ºC)
Characteristic
Symbol Min
Typ
Max
1.0
Units
Vdc
Vdc
Vdc
Vdc
µA
Conditions
Input Low Voltage
Input High Voltage
Input Low Voltage
Input High Voltage
VIL1
VIH1
VIL2
VIH2
IIL
-
-
-
-
-
Note 1
2.0
-
-
1.0
-
Note 2
2.2
-66
Input Low Current (@VIL =
VSS)
-5
For pins with internal Pull up resistors,
Note 1 and Note 2
Input High Current (@VIL =
VDD)
IIH
5
µA
Tri-State leakage Current
Dynamic Supply Current
Static Supply Current
Input pin capacitance
Output pin capacitance
Pin Inductance
Ioz
Idd3.3V
Isdd
-
-
-
-
-
-
-
-
-
-
-
-
10
160
400
5
µA
mA
µA
pF
Note 3
PwrDwn = LOW, Note 3
Cin
Cout
6
pF
Lpin
7
nH
Note1: Applicable to input signals: Selq, Selr, Sels and , PwrDwn.
Note2: Although internal pull-up resistors have a typical value of 250K, this value may vary between 200K and 500K.
Note3: All outputs loaded as per table 3.
Output name
Max Load (in pF)
REF(1,2), 48MHz(1,2)
3V66(1:6), PCI(1:12)
20
30
Table 3.
Note:
All Buffer characterization data is specified with all outputs connected to those rated loads simultaneously.
Cypress Semiconductor Corporation
525 Los Coches St.
Document#: 38-07076 Rev. **
5/9/2001
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
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