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B9852AYB 参数 Datasheet PDF下载

B9852AYB图片预览
型号: B9852AYB
PDF下载: 下载PDF文件 查看货源
内容描述: [PLL Based Clock Driver, PDSO56, SSOP-56]
分类和应用: 驱动光电二极管逻辑集成电路
文件页数/大小: 13 页 / 140 K
品牌: CYPRESS [ CYPRESS ]
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PRELIMINARY  
B9852  
High Performance Pentium III Clock Buffer  
2-Wire SMBUS Control Interface  
The 2-wire control interface implements a write slave only interface according to SMBUS specification. (See fig5,  
page6). The device can be read back by using standard SMBUS command bytes. Sub addressing is not supported,  
thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control interface allows  
each clock output to be individually enabled or disabled. 100 Kbits/second (standard mode) data transfer is supported.  
During normal data transfer, the SDATA signal only changes when the SCLK signal is low, and is stable when SCLK is  
high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the  
start of a data transfer cycle. A low to high transition on SDATA while SCLK is high indicates the end of a data transfer  
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a  
transfer cycle is a 7-bit address with a Read/Write bit (R/W#) as the LSB. R/W# = 0 in write mode.  
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal  
on the SDATA wire following reception of each byte. The device will not respond to any other control interface  
conditions, and previously set control registers are retained.  
Serial Control Registers  
NOTE: The Pin# column lists the affected pin number where applicable. The “@ Power Up” (@Pup) column gives the  
state at true power up. Bytes are set to the values shown only on true power up.  
The serial bits will be read by the clock driver in the following order:  
Byte 0 – Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte 1 – Bits 7, 6, 5, 4, 3, 2, 1, 0  
Byte N – Bits 7, 6, 5, 4, 3, 2, 1, 0  
All unused register bits (reserved and N/A) will be designated “don’t care”. They must be sent and will be  
acknowledged  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07076 Rev. **  
5/9/2001  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
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